Traditional electronics are assembled as a planar arrangement of components on a printed circuit board (PCB) or other type of substrate. These planar assemblies may then be ‘plugged’ into a motherboard or card cage creating a ‘volume’ of electronics. This architecture is common in many military and space electronic systems as well as large computer and telecommunications systems and industrial electronics. The individual PCB assemblies can be replaced if defective or for system upgrade. Some applications are constrained by the volume or the shape of the system and are not compatible with the motherboard or card cage architecture. Examples include missiles, camcorders, and digital cameras. In these systems, planar rigid-flex substrates are folded to create complex 3-D shapes. The flex circuit serves the role of motherboard, providing interconnection between the rigid boards. An example of a planar rigid – flex assembly prior to folding is shown in figure below.
In both architectures, the interconnection is effectively 2-D.
One of the earliest examples of 3-D electronics was stacked dual-in-line packages (DIPs) containing memory. Memory has a high degree of parallelism in the interconnections between devices. DIPs were stacked on top of each other. With the leads overlapping, the leads were joined by soldering, creating parallel connections to all devices in the stack. The ‘chip select’ pin on each package had to be individual connected – this could be accomplished with jumper wires. This is an example of Package Stacking. Irvine Sensors pioneered Die Stacking, creating cubes of memory for solid-state data recorders. Memory die were stacked using an adhesive to form a cube. The edges of the cube were then polished to expose the edges of the wire bond pads or pad extensions. The edges of the cube were metallized and pattered, electrically interconnecting the memory die. An example of a memory cube is
With the rapid growth in portable consumer electronics, most notably the cell phone, the need to decrease size and weight while increasing functionality has been driving the electronics industry to widespread use of die and package stacking. Many approaches have recently been developed for die and package stacking.
At the next higher level of integration, 2-D modules are being stacked to create 3-D module assemblies. One example of this is the Vertical InteGration for Opto and Radio (VIGOR) subsystems illustrated in figure. This was a European Union funded 3-D Integration project. The concept is similar to the Irvine Sensors die stacking approach. Individual circuit boards are assembled, tested, stacked, molded, and the edges of the cube are metallized and patterned to form the z-axis interconnections.
The ultimate in 3-D integration is wafer stacking. The technology is being developed for image processing systems. Image sensors are 2-D arrays of sensors or pixels. In current architectures, the information from each pixel must be clocked to the edge of the array before processing. For large arrays, this serial processing does not permit real-time imaging. In wafer stacking, the processing elements are fabricated on wafers to be bonded below the sensor array. Each pixel has a processor associated with it, resulting in a massively parallel system.
The primary driver for 3-D electronics has been to reduce size and weight. Recently, 3-D electronics are being developed to reduce signal propagation delay by locating devices closer together. The challenges faced by 3-D integration are: limits in interconnectivity in the z-axis, yield, and thermal management. Many of the 3-D approaches provide z-axis interconnection along the perimeter of the assembly and not a true 3-D interconnection distributed within the volume of the assembly. This perimeter routing limits the ability to route interconnections and also increases the signal path (all signals have to come to the edge). Pre-test and high assembly processing yields are critical to achieving a high final yield. In most 3-D constructions, rework is difficult or impossible. Finally, heat transfer to the surrounding environment by convection and conduction is limited by the available surface area. 3-D electronics have the potential to dramatically increase the heat density while simultaneously dramatically reducing the surface area of the assembly. Thus, not all electronics will be conducive to 3-D integration without significant investment in thermal management technologies.
Package stacking is the simplest to implement. It does require internal and/or external package modification. Parallel I/O connections such as Address and Data as well as Power and Ground can share common leads for all devices. However, Chip Select for each package must be on a different pin.
The figures below illustrate stacking of memory TSOPs to create a 32 bit wide data bus using two 16 bit devices. In this case a perimeter substrate is used to interconnect the two TSOPs and provide Chip Select and other electrical signal routing. The solder balls shown as 67 through 87 in Figure provide the electrical contacts for the extra routing required.
With the wide-spread usage of ball grid array (BGA) and chip scale packages (CSPs), stacking of these packages has become common in the portable electronics industry figures below show a stacked rigid substrate CSP figure below shows a 4 package stack with flex substrate CSPs. The stacked packages can also contain stacked die within one or more of the packages as shown in figure. The inclusion of a substrate (rigid or flex) in the package provides the option for the necessary routing changes for electrical connections within the stack. The packages can be stacked by the package manufacturer and assembled as a single unit by the PCB assembler or the packages can be stacked and assembled to the PCB simultaneously by the PCB assembler. With solder ball based packages, the upper packages can be assembled with a flux dip, placement and reflow – no solder paste is required.
Irvine Sensors has developed technology to process existing packages into thin stackable layers. Similar thinning of BGAs with deposited surface metallization on the thinned layer to route from the die I/O to the layer edge has also been described by Irvine Sensors. Once the thinned layers are stacked and molded, the edges of the cube are metallized to connect between layers.
Benefits of Package Stacking: The primary advantages of package stacking are the reduction in substrate area, decreased interconnection lengths and the ability to pre-test packages before stacking. Solberg has discussed the increased electrical performance with packaging stacking. The net volume and weight are not reduced by package stacking (except in the Irvine Sensors approach), but the board area occupied by the stack is less than that required to arrange the individual packages in an area configuration. The electrical interconnection length between packages in a stack is less than the length that could be achieved with individual packages arrayed in a planar configuration, decreasing propagation delay. A major advantage of this approach is the ability to pre-test and burn-in devices prior to stacking. Depending on individual die yield this can have a significant impact on the yield of the stack. Rework of a package within the stack is possible, but is much more complicated than removal of a single package configuration.
Limitations of Package Stacking: BGAs and CSPs must be designed for package stacking to allow contact pads for assembly on both the top and bottom side of the package substrate. In the case of surface mount lead frame packages, the lead length must be increased to allow lead-to-lead contact when stacked or an interposer substrate must be used. The package internal routing must also be changed to accommodate the special electrical signal routing requirements for package stacking. While BGAs and CSPs typically provide full area array I/O interconnections, packages designed for stacking are restricted to one or more rows of perimeter I/O connections. Thus, with the exception of the bottom package, the I/O count is limited or the size of the package must be increased to allow extra rows of I/O’s. Stacked packages are most appropriate for memory or memory with one high I/O count device (microprocessor, DSP, ASIC) on the bottom. Since package stacking requires the complete packaging of the individual die, there is no cost savings in the packaging process. The extra processing in the Irvine Sensors approach adds cost, but reduces height and weight. Since heat removal through the leadframe or the solder balls to the PCB is the predominate path for conductive heat flow, stacking packages increase the thermal path length for the top package and increases the heat flux through the solder balls or leadframe of the lower packages. Also, thermal solder balls, commonly used in BGAs can only be used on the bottom package. With packages stacked, the heat transfer by natural convection from the package surface is reduced for the lower packages in the stack. Package stacking is typically restricted to low power dissipation applications and the highest power dissipating package is placed at the bottom of the stack.
Reliability: Stacked packages utilize commercial-off-the-shelf (COTS) packaging which establishes the reliability baseline. The unique reliability issues with package stacking are assembly quality and mechanical shock and vibration effects. Warpage of area array packages and the resulting impact on solder joint shapes during package stacking must be considered. If one package warps concave and one package warps convex, the solder joints will be elongated or opens may even occur during assembly. The reliability of these elongated solder joints is a concern and must be investigated. The issue of warpage is dependent on the package style, materials and construction processes and will require investigation on an individual basis. Increasing the mass and height of the stack assembly will potentially impact the reliability in a mechanical shock and vibration level. Currently, most package stacks are only two packages high and with the use of thin packages, the resulting height and mass is very similar to conventional non-stacked packages. Little data is available on mechanical testing of more than two packages stacked. This area will need further analysis and experimentation. The following tables provide published reliability data for different stacked packages. The testing is not to failure, so failure statistics can not be used to predict failure rates.
Amkor has studied the thermal cycle reliability (-40 o C to 125 o C, 1 cycle/hour) of two stacked CSPs (rigid substrate) versus a single CSP. The figure below is a Weibull plot of two stacked CSPs and a single CSP assembled on one side of a laminate substrate. As can be seen, the mean life is slightly lower for the two stacked CSPs. The figure below compares the results (modeled and measured) mean life with single CSPs and two stacked CSPs on a single side (SS) of the laminate and on both sides (DS). In both cases, the thermal cycle reliability of the two stacked CSPs is less than that of the single CSP. Stacking CSPs leads to an increase in assembly stiffness, which reduces reliability. Stacking additional CSPs would lead to a further increase in stiffness.
Die Stacking
The most rapidly growing segment of the 3-D market is die stacking. The earliest implementations pioneered by Irvine Sensors involved stacking die using adhesives to create a cube, polishing the edge(s) to expose the perimeter wire bond pads or pad extensions, then passivation and metallization of the cube edges to provide z-axis interconnectivity . The resulting 3-D memory cubes were used for solid-state data recorders. Caterer, et.al. used a thick polyimide layer to redistribute the memory die I/O to the edge of the die for routing along the cube edge. The cube was assembled to the package using Sn/Pb solder bumps.
Lea, in conjunction with Irvine Sensors, developed a 3-D massively parallel processor die stack. The die I/O were re-routed to two sides of the die using thin film gold metallization. The wafers were then thinned and diced. Using adhesive, the die were laminated between top and bottom ceramic substrates (AlN).Two sides of the cube were polished, exposing the re-routed I/O. The edges were then metallized. The ceramic cap chip provided routing for wire bond pads – wire bonds are used to electrically interconnect from the cube to the package or substrate.
Irvine Sensors develop the NEO stack technology to allow stacking of different size die and multiple die per layer. A single die layer is illustrated in the figure, while a two die layer is shown in the figure below the latter. Known good die are stud bumped using a gold wire bonder. The die are then arrayed and potted to create a NEO wafer. Polyimide and thin film metallization are patterned on the surface of the NEO wafer. The NEO wafer is then diced. A thin layer of epoxy is used to bond the stack of NEO die as illustrated in figure. The stack is then ground on the edges to expose the perimeter traces and metallized providing provide z-axis interconnections.
Val, et al. has developed a die stacking technology based on wire bonding die to a flex substrate. Perimeter probe pads on the substrate facilitate die testing and burn-in. Tested die are then stacked and molded into a cube. A diamond saw is used to cut the edges of the cube, exposing the wire bond wires. Electroless Cu/Ni/Au is used to metallize the edges of the cube. Patterning of the edge metallization is accomplished with a laser.
Die stacking to create cubes can package many die in a small volume, but requires significant post die processing. The primary die stacking technology in volume production today involves stacking two or more thinned die and wire bonding them into a package (TSOP, BGA, CSP). Examples of this type of die stacking are illustrated in figures. Tooling is used to allow double-sided die attach and wire bonding prior to transfer molding in a TSOP. An alternate approach, where two lead frames are used. After wire bonding, the two lead frames are joined by either Ag-Sn solder or Ag-to-Ag thermocompression bonding. Another illustration is when die attach of one die on the surface of another and wire bonding to a common substrate prior to transfer molding. Combining flip chip and wire bond assembly as illustrated in figure allows a high I/O count area array die to be flip chip assembled as the bottom die in a two die stack. Alternately, if the flip chip die is smaller than the wire bond die, a redistribution layer can be processed on the wire bond die and the smaller die flip chip attached on top of the wire bond die . Another figure illustrates combining stacked and non-stacked die in a common multichip package.
The key technologies for die stacking are wafer thinning, thin die handling and advanced wire bonding. Mechanical, Chemical-Mechanical, Chemical, Plasma and combinations of these are used to thin silicon die. 100$\mu$m thick die are commonly used today and 75$\mu$m and thinner die are beginning to be used. However, Sempek has identified issues with refresh interval degradation with thinned memory die. The exact cause has not been identified, but there is concern over contamination from the Chemical-Mechanical Polishing (CMP) slurry. According to Sempek, other potential issues with thinning include single bit failures, reverse tunneling effects, and punch through. Lépinois has studied the effect of thinning on the electrical characteristics of transistors. The performance of bipolar transistors is only affected in marginal cases when dislocations are introduced by the thinning process. The effect was only observed at low currents level, below normal operation levels. The only effect observed in MOS devices was self heating in power MOS transistors due to the replacement of Si with polymer, increasing the thermal resistance for heat transfer by conduction. Advances in wire bond loop control have made complex wire bonding of stacked die possible. To maintain low loop heights, reverse wire bonding (1st wire bond on package substrate, 2nd wire bond on die) is often used. To avoid shorting of the wire to the Si die surface, a stud bump is bonded to the I/O pad and the 2nd wire bond is made to the top of the stud as shown in Figures. Wire bonding to overhanging, thinned die has also been developed. Wire sweep during transfer molding must be considered in die stacks with a high density of closely spaced wire bonds.
Epoxies and silicone adhesives are used for die attachment. Key characteristics of die attach adhesives for stacked die include:
1.Non-abrasive to avoid damage to die passivation (polyimide, silicon nitride, etc.)
2.Low stress – increasingly important for low-k dielectrics used in the multilevel metal systems of advanced semiconductors to reduce on-chip propagation delays. These low-k dielectrics have lower mechanical strength than traditional dielectric materials.
3.High thermal conductivity to transfer heat through the stack to the substrate or lead frame.
4.Controlled bond line thickness to maintain a controlled spacing between die. Controlled bond line thickness is important for electrical isolation, stack thickness control and to prevent wire bond damage.
When assembling same size die, silicon spacer die are often used to maintain adequate spacing between die to prevent damage to the wire bonds. In same size die assemblies, each die must be placed and wire bonded before the next die is placed.
An alternate die stacking option is to assemble die to a flex substrate and then fold the flex to create a 3-D stack. Auburn University , Tessera and the Project FLEX-Si ´Ultra-thin Packaging Solutions Using Thin Silicon have pioneered folded flex technology. The work by Johnson and by the European Program focused on flip chip based die assembly, while Tessera has extended their $\mu$ BGA single chip packaging technology to create folded flex assemblies. The figure below shows the original four die stack demonstrated by Johnson, et al. The four die were assembled to the flex substrate using a patterned isotropic conductive adhesive. Once assembled, the flex substrate was cut and folded to create the 3-D stack. Non-conductive adhesive preform sheets was used to adhere the layers of the folded stack. The Tessera Z ® $\mu$ 3-D folded three die stack technology is show in Figure. Figure shows the substrate details. Tessera uses either the wire bonding or the lead bonding technology developed for their BGA ® $\mu$ single chip packaging technology. In the wire bond approach, wire bonds are from the die surface to the pads on the flex substrate through a window opened into the flex substrate. After wire bonding, the wire bonds are encapsulated. For the lead bond technology, the leads are patterned as part of the flex substrate. The polyimide is then etched away, creating the bond window. The bond windows in the substrate are shown in Figure. Using a conventional wire bonder with a modified bonding tool, force is applied to the lead causing it to break in the narrow region. Ultrasonic energy is then used to bond the lead to the die bond pad.
A primary advantage of folded flex technology is the ability to use area array die. However, the chip-to-chip routing is effectively 2-D. Furthermore, two or more metal layer flex substrates are expensive and the number of suppliers is limited. For the ultimate in die stacking, thru-silicon vias can be fabricated to provide electrical paths through the silicon die. With I/O pads on both sides of the die, the die can be stacked and interconnected without wire bonds. Using a thin (1.5$\mu$m) Sn2.5Ag cap on the Cu thru-vias, the electrical interconnects from die to die are formed on a heated flip chip bonder by converting the Cu and Sn into Cu 3 Sn intermetallic. The process is illustrated in figure below. Vacuum encapsulation is used to underfill between the die in the stack. A four die stack is shown in Figure. This process requires significant backend wafer processing. It is possible for high volume devices that benefit from 3-D stacking such as memory, that thru-silicon vias will be integrated into the memory design and wafer fabrication in the future.
Benefits of Die Stacking: Die stacking provides a significant decrease in size and weight and reduces next level assembly costs. It is particularly well suited for memory or memory in combination with a single microprocessor or digital signal processing chip. Two die wire bonded stacks are in high volume production for cell phone and other portable products and the die count is trending upward. With die thinning, stacked die packages are no thicker than traditional single chip packages. Die stacking reduces signal path length compared to individual packages.
Limitations of Die Stacking: The key limitations to die stacking are die yield and thermal dissipation. The thermal performance is limited by the package (BGA, CSP, etc.). The total power dissipation for all die in the stack is limited to the power dissipation limit of the same package with a single die. In the case of one low power die and one high power die, the lower power die may actually run hotter due to heat transfer from the higher power die. A microfluidic-thermoelectric cooler has been proposed to remove the heat from stacked die. CVD diamond heatspreader layers have also been investigated. Thermal management is becoming a critical factor in electronics packaging for both single and stacked die.
Acceptable package level yield relies on either high die yield or testing for known good die. Rework within the package is not practical. To address this yield issue, Package-in-Package (PiP) has been introduced. As illustrated in figure below, the concept is to integrate a pre-assembled and pre-test package into a 3D stack. Wire bonds are used to connect the top package to the base package substrate.
Tessera has developed a PiP approach using a foldable flex tab integrated into the fabrication of one package to provide interconnection to the second package. The concept is illustrated.
Reliability: The reliability of the stacked die packages is similar to that of the equivalent single die package. Nakanishi has reported similar reliability for two die TSOPs. Fukui, et al has shown similar thermal cycle reliability for two and three die stack (wire bonded) CSPs. The 3-D stacking technology developed by Val and now manufactured by 3D-Plus has been through extensive reliability testing.
3-D Multichip Modules
With significant funding from DARPA in the 1990’s, there was significant development in 2-D multichip modules. A convergence of chip-on-board, cofired ceramic and deposited multilayer thin film technologies lead to MCM-Laminate (MCM-L), MCM-Ceramic or Glass/Cermic (MCM-C) and MCM-Deposited (MCM-D) approaches respectively. There were also combinations of these, i.e. thin film layers deposited on top of cofired ceramics (MCM-C/D), etc. These technologies provided a high density of 2-D interconnections and with the elimination of individual chip packages a high density of die, again in a 2-D array. These technologies are in use today, with few chip MCM-L dominating the commercial market. The need for known good die and the associated yield favors few chip modules. Increasing the number of die per module decreases overall module yield unless the certainty of know good die increases. MCM-C and MCM-D are typically hermetic packages and have been used for space applications. The Jet Propulsion Laboratory is developing a chip-on-board (MCM-L) assembly for the Mars Science Laboratory.
MCM-L, MCM-C, and MCM-D are all examples of chips last, i.e. the interconnect substrate is fabricated and then the die attached to complete the module. Auburn University, General Electric and Lockheed-Martin have each developed ‘chip first’ technologies. The original General Electric concept is illustrated in figure . The process flow is illustrated in figure. Die were placed in machined cavities in a ceramic substrate. A polyimide film (Kapton) was overlaid and adhered to the surface of the die and the ceramic. Vias were laser drilled down to the I/O pads on the die. Thin film metallization was used to interconnect the die. The film, laser drilling and metallization steps were repeated to create multilayer interconnections. General Electric has developed several variations of this basic approach for different applications. The challenge of known good die is more critical in the ‘chips first’ approach, since rework is limited.
A number of approaches to 3-D multichip modules have been developed. Jensen, et al developed a two-sided MCM-C module. Note the MCM also contains stacked die. The ability to process vias through the layers of the ceramic substrate provided front-to-back electrical interconnections. Clarke, et al. also developed a two-sided MCM-C using a 23 metal layer cofired aluminum nitride substrate.
Ceramic and laminate based multichip module technologies providedirect front-to-back electrical interconnections, allowing double sided assemblies. However, this only results in two active levels of devices, a limited 3-D capability. A number of approaches have been developed to create 3-D MCMs with multiple active layers. These are primarily based on edge connections. One pioneer in this field is 3D-Pus (BUC, France). The process sequence is shown in figure. The circuit is partitioned into layers. Each layer is designed onto a flex epoxy/glass substrate and may contain passive components, packaged chips, chip-and-wire, flip chip die and other elements. An example substrate layer is shown in. “Flying leads” are created in the substrates for interconnections that must interconnect between layers. Once the substrate layers are fabricated and the devices are assembled, they are electrically tested. Pads are designed along the perimeter of the substrate to facilitate electrical testing. The individual layers are then stacked and molded into a cube. The cube is sawn to expose the “flying leads” as shown in figure. Plating (Ni/Au) and laser patterning are used to define the electrical interconnections along the cube edge between layers. The Vertical InteGration for Opto and Radio (VIGOR) subsystems illustrated in figure were developed based on the 3D-Plus technology with funding from the European Union 3-D Integration Project. The project focused on printed circuit board dielectric materials and “flying lead” formation, molding compound materials and edge metallizations and patterning technologies.
General Electric has developed a 3D MCM technology based on their ‘chips first’ HDI MCM technology. The concept is illustrated in figure and the process sequence is illustrated in Figure. Polyimide film with laser based vias and copper interconnections are used to make cube edge connections between layers. A close-up is shown in Figure. An example 3D MCM is shown in Figure.
Pienimaa, et al. has developed a 3-D MCM stacking approach using Sn/Ag plated plastic balls around the perimeter of the MCMs to interconnect between MCMs. The process sequence is illustrated in Figure
Fuzz buttons have also been used to interconnect stacked MCMs. The structure is illustrated in Figure. Next Figure illustrates the stack-up sequence. The MCM substrate was polycrystalline diamond with thin film copper and polyimide layers fabricated on both sides. The Fuzz Button Board was a plastic retainer with 7200 holes. The gold plated fuzz buttons (Brillo Pads) were inserted into these holes. Attached is a photograph of the Fuzz Button Board. Fuzz buttons provide a separable connection between the MCMs, providing an option for repair. As illustrated in figure, compression bolts are required to maintain electrical contact between MCMs through the fuzz buttons.
Thales Microwave has developed a 3D T/R module. The construction is illustrated in figure below. The individual MCM layers are MCM-D with embedded $\ Ta_2 O_5$ capacitors. Electrical connections between MCM layers are made with fuzz buttons.
The limitation of the edge routed 3D cubes is the number of interconnections available between layers and the requirement that signals be routed to the edge of the cube before routing to other layers, which adds signal delay. IMEC in Belgium has developed a 3D chip stacking technology with the potential for extension to 3D MCMs with z-direction connections distributed over the area of the MCM. The basic concept is shown in Figure. The technology requires ultra-thin (~10-15 &\mu$m) silicon die. The process sequence is shown in Figure. Next figure shows a photograph of interconnections to a 15$\mu$m thick die, while next figure shows a cross section of a single die layer MCM. Since this is a sequential built-up process, known good die and high process yields are required. Thermal modeling of the structure has been performed. The die are embedded in BCB which has a low thermal conductivity. Thermal vias and metal heat spreaders can be used to improve thermal performance. Leseduarte, et al., have evaluated the stress on the thin silicon die assembled into the structure. The model results indicate a wide range of design freedom.
Benefits of 3D MCMs:
3D MCMs provide a significant increase in functional density, decreasing size and weight. Interconnection lengths between devices are reduced, increasing signal speed. MCMs allow mixing and matching of different component technologies (digital, analog, rf, optical, Si, GaAs, passives, sensors, etc).
Limitations of 3D MCMs:
Increasing functional density results in increasing power density, thus thermal management is an issue. Diamond substrates and integrated heat pipes are potential solutions to address heat removal, but additional work is required in this area for higher power 3D MCMs.
3D MCMs can potentially integrate a large number of die. As with other 3D technologies, die yield and know good die are a critical issue for 3D MCMs. Repair is possible in some 3D MCM technologies during the assembly process, but not after final assembly. Thus, system partitioning and good fault cover testing at the sub-assembly level is also important.
3D MCMs are custom products, thus the supplier base is much smaller than for stacked die or stacked packages. Furthermore, the 3D MCM technology used is specific to the supplier, resulting in effectively a single source situation.
Reliability of 3D MCMs: Reliability data is specific to the individual 3D MCM technologies. Although not completed at the time the paper was written, the Honeywell double sided MCM-C was to be screened for Space applications [Jensen.pdf]. The 3D-Plus MCM technology has been qualified by the European Space Agency [Val-1.pdf]. The approval test plan is shown in figure below. The 3D MCMs passed the tests outlined in the plan. The VIGOR 3D test vehicle pasted 500 thermal cycles (-55 o C to +125 o C) with the selection of the proper substrate and molding compounds [Alexandre.pdf]. Some material combinations tested in the experiment did not survive 500 cycles. The General Electric 3D MCM technology was also developed targeting military and space reliability requirements. The GE 3D MCMs have passed 100 cycles from liquid nitrogen (-193 C) to +125 C, 300 cycles from -65 o C to +150 C and 22 hours of water soak at 85 C.
Wafer Stacking
DARPA has funded the Vertically Integrated Sensor Arrays (VISA) program to develop stacked wafer technology. The applications driver for this technology is to develop real-time large area sensor arrays. The information in each pixel must be serially transferred to the edge of the array for processing. This limits the speed of large arrays. In the VISA program, wafers are to be stacked behind the sensor array so that pixel information can be transferred downward for processing in a massively parallel fashion. As shown in Figure, multiple sensors layers can also be included for visible and IR detection. The resulting imaging system would be similar to human vision.
The MIT Lincoln Laboratories 3D technology is illustrated in Figures. The top wafers (wafers 2 and 3) are silicon-on-insulator (SOI) and in the process the underlying silicon is removed, leaving isolated devices surrounded by oxide. In the original process, adhesive (epoxy) was used to bond the wafers. This limited processing temperatures to <200 o C. A low temperature oxide bond is now used by MIT Lincoln Laboratories, allowing higher temperature processing in subsequent steps. Low pressure chemical vapor deposited (LPCVD) oxide layers deposited on each wafer are used as the bond layers. The two LPCVD oxide layers are bonded together at 275 o C for 10 hours. Chemical vapor deposited (CVD) tungsten plugs are used for the wafer-to-wafer interconnection. In the last step, bond pads are opened to allow packaging of the 3D device by conventional wire bonding.
A number of research groups are working to develop 3D wafer stacking technology including IBM [Guarini.pdf], Tezzaron Semiconductor, the University of Arkansas, Ziptronix, and Raytheon Visions Systems/University at Albany. The Raytheon/University of Albany approach uses benzocyclobutene as the adhesive layer between wafers. Tezzaron, the University of Arkansas and others are developing through wafer technology with plated copper interconnections. A cross section of the Tezzaron Cu interconnects is shown in Figure
Benefits of Wafer Stacking:
Wafer stacking provides a true 3-D interconnect structure, allowing highly parallel signal processing. It is particularly suitable for image processing, and is being considered as a way to extend Moore’s Law for high performance processors and memory. The electrical performance benefits of short, 3-D interconnections have also been modeled for a RIC Processor/Cache System.
Limitations of Wafer Stacking:
Wafers must be designed for compatibility with wafer stacking. Thus, the approach is not suitable for low volume applications unless it is an extremely high value added application. As with other 3-D stacking technologies, thermal management will be a major challenge. In the MIT-Lincoln Laboratories structure, the SOI transistors are surrounded by silicon dioxide, which has a low thermal conductivity. Rahman has shown that the power dissipation in 3-D ICs is lower due to less parasitic interconnection capacitance. Thus, lower power operation is one advantage and potential thermal benefit of 3-D wafer stacking.
Yield will be a major challenge. Each wafer will have an individual yield and in many cases, a good die on one wafer will align with a defective die on another wafer in the stack. Wafer mapping and sorting may be used to optimize stacked yield. Ziptronix has developed a hybrid approach to achieve higher final yield. In this approach, pre-tested die are stacked onto a pre-tested base wafer. Ziptronix has patented a pre-treatment that allows room temperature, covalent oxide-to-oxide bonding of the die to the base wafer. Figure shows an ‘over the edge’ interconnect of a 10$\mu$m thick die to the base substrate. A planarization step allows thin film processing of the interconnections. Ziptronixs has also developed thru-wafer interconnections as shown in Figure
Klumpp, et al. have also developed a chip-on-wafer approach. The process flow is shown in Figure. The process uses W metallized vias through thinned die to achieve back side electrical contact. Cu-Sn intermetallic bonding is used to bond the die to the wafer and to provide electrical interconnections.
