Friday, April 15, 2011

3D IC packaging necessary to maintain Moore's Law ?

A 3D IC technology was viewed as necessary to maintain integrated circuit performance on the path described by Moore’s law. One issue was the projected increase in chip-operating frequencies that would lead to different clock rise and fall times within a chip as shown in



Numerous theoretical studies examined the performance of 3D ICs as a function of the number of active tiers and the placement of memory, logic, and other functions among and within the active tiers, but early attempts to build even rudimentary 3D ICs were unsuccessful. Those 3D ICs were constructed using epitaxial overgrowth or polysilicon deposition to stack silicon layers, but the transistor characteristics or transistor densities were unsatisfactory. Attempts to create vertical connections through silicon chips were frustrated by the inability to uniformly thin the chips to less than 50 mm and to insulate deep cuts etched through the thinned chips. At the same time IC technology developments led to tighter design rules and improved transistor performance so that IC progress continued to satisfy Moore’s Law. Within the last 10 years it became clear that Moore’s law could not be met solely by transistor design and fabrication innovations. Therefore, the development of an alternate technology to design and construct microelectronic systems as 3D devices became essential.

TSV based 3D Integration future of semi-conductor packaging ?

Theoretical studies in the 1980s [A 3D IC technology wasAkasaka Y (1986) Three-dimensional IC trends. Proc IEEE 74(12):1703–1714] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose placement within the tiers is discretionary. The term “tier” is used to distinguish the transferred layers of a 3D IC from design and physical layers and is the functional section of a chip or wafer that consists of the active silicon, the interconnect, and, for a silicon-on-oxide (SOI) wafer, the buried oxide (BOX).

The basic features of a 3D IC are shown in the figure in a symbolic drawing along with a cross-section of an actual 3D IC.



The TSV (through silicon via) is an essential feature of the 3D IC technology and is the vertical-electrical connection formed between tiers and through silicon or oxide. A TSV is formed by aligning, defining, and etching a cavity between two tiers to expose an electrode in the lower tier; lining the sidewalls of the cavity with an insulator; and filling the cavity with metal or doped polysilicon to complete the connection.

3D stacked Integrated Chip Stacking

Keeping up the trend of integration and power consumption reduction in the era of slower scaling clearly requires a new set of solutions. Chip stacking is seen by many in the industry as the technology that will enable the necessary continuum in the trend for increased integration. It is a class of solutions that has emerged as a combination of technology scaling and packaging techniques. Various flavors of chip stacking technologies have been proposed and some of them have been in production for a number of years. Stacks of packaged die interconnected using wire-bonding, flip-chip bumps or ball grid arrays, wafer-level packaging of chip stacks, and other techniques to stack and interconnect chips have been used to create products in the past. All these techniques manage to integrate more functionality in a single package and they reduce the power consumed in communication between chips since they substitute Printed Circuit Board connection with wire-bonds or solder balls which have much better electrical characteristics. To push the boundary of integration and power consumption reduction, chip stacking has taken another step. 3D stacked integrated circuit (3D SIC) is a chip stacking technique where the vertical conductors are embedded in the substrate during the manufacturing of the wafers in the foundry. This enables a very high interconnection density between neighboring die in the stack with low-capacitance interconnects.




The above figure shows how the aforementioned chip stacking techniques score on a number of axes. Technology integration refers to the capability of integrating die or chips built using different process technologies. Interconnection density refers to the number of vertical connections that can exist per unit of area. Integration density quantifies the capability of the technique to integrate a lot of functionality in a small volume. Performance refers to latency of vertical interconnections and form factor refers to the size of the final product per functionality embedded. 
Multi-chip-modules (MCMs) which incorporate many chips in a package side by side can integrate very heterogeneous chips at a good, i.e. low, cost but score rather low on the other axes, because it is still a solution that requires a lot of area and interconnections need to traverse large distances.
Chip stacks interconnected with wire-bonds are relatively good along all axes but do not excel anywhere. They are better than MCMs in integration density and form factor as they can pack more functionality in smaller volume and faster since the resulting wire bonds have better electrical characteristics. But, wire-bonding suffers from scalability issues. Wire-bonds can only connect I/O pins on the periphery of chips and the available real-estate there is limited. Hence wire-bonding cannot offer a significant increase in interconnection density.

Ball grid array (BGA) stacks interconnect the different chips in the stack using arrays of solder balls. They improve on technology integration, but they are less cost-efficient compared to wire-bonded stacks. One of their main advantages includes the better electrical characteristics of the balls compared to the wire-bonds. This is especially useful in power delivery; for instance, solder balls enable better power delivery to power-hungry blocks with much supply voltage variations.

Wafer-level packaging (WLP) goes a step further in form factor and integration density. It uses large vias through the silicon substrate to interconnect the different die. This increases the integration density and improves the form factor of the final stack compared to BGA implementations.

3D stacked integrated circuits (3D SIC) or 3D integrated circuits (3D IC) technology is the next generation in chip stacking technology. Bare die are stacked and are interconnected using vias through the substrate with very fine pitches. It is today the only practical solution that provides the capability to interconnect different die with tens of thousands of interconnects. Even though it is currently still an expensive process, it offers advantages in integration density as it results in the smallest volume, the highest performance, the smallest final form factor for the packaged stack and has by far the highest interconnection density between the die in the stack.

Semi-Conductor Industry and Need for Integration

The semiconductor industry has been one of the main enablers for the boom of the information technology revolution that we have witnessed in the beginning of the twenty-first century. Each new generation of consumer electronics devices that hits the shelves boasts more features and functionality, better connection to other devices, lower cost, and better power efficiency per function. An excellent example of this trend is the evolution of the mobile phone since its proliferation in the end of the last century. Mobile phones started out by offering the minimal functionality of voice calling, then evolved to offering short messaging services and since then the features have kept piling up. State-of-the-art mobile phones in 2010 are in reality computing platforms offering extreme power efficiency, small form factor, and low cost for the offered functionality, which includes connectivity with virtually all known standards, high definition video decoding, social networking, office productivity suites, GPS plus any application the software community generates!
Consumers have gotten used to these trends and expect a further improvement with every generation of products coming out, which puts pressure on the consumer electronics manufacturers to deliver on these expectations. This translates to a continuous pursuit for low-cost and low-power integration. More and more functionalityneeds to be integrated into fewer chips to reduce the component count and the real estate of printed circuit boards. Chips with increased functionality need to be shrunk in order to reduce their cost and power consumption.
The key driver of this continuous improvement has been semiconductor process technology scaling that has shrunk the physical dimensions of transistors and interconnections to miniscule sizes, transistor channels measure a few tens of nanometers across. This miniaturization has increased the functionality per unit of area in chips by about a factor two every 3 years for the past five decades; the first integrated circuits in the 1960s comprised a few transistors, state-of-the-art integrated circuits in 2010 measure more than a billion transistors on a single die. Shrinking transistor sizes has provided other benefits as well; smaller transistors have lower capacitances so they are faster and consume less power each. Note that even though power per transistor is reducing, the increased level of integration is packing more of them into smaller spaces, elaborate design solutions are required to keep the chip-level power consumption low. This has fueled the evolution of electronics for decades.
This miniaturization by physical dimension scaling is slowing down as transistor channel lengths hit the range of 20–30 nm. Process technology is running into problems such as process variability, increased leakage currents, lithography limitations. Designers are forced to embed worst-case margins in the chips in order to work around these issues, which leads to an increase in power consumption. Furthermore, manufacturing ever larger chips has a negative impact on the production yield; fewer of them turn out to be fully functional. A lot of research effort is invested worldwide to overcome these problems and enable the technology scaling to continue unabated. But it is very doubtful whether technology scaling alone can keep delivering the rate of improvement it offered in the past decades.
Another source of increased integration has been advances in chip packaging. In the early days, packages housed one chip each. Later on multiple chips were being integrated in one package in various configurations, either side to side or on top of each other, and were interconnected using small wires inside the package. State-ofthe- art packaging techniques include System-in-a-Package, which integrates multiple chips of heterogeneous functionality and process technology into a single package interconnected with wire bonds.
The benefits offered by technology scaling and packaging advances are coming to an end. The desire for further integration and power efficiency is not however. Consumers still want more functionality at lower cost and higher power efficiency, probably more than ever

3D Integration

There are several driving forces for 3D integration. The potential benefits include higher performance, reduced power requirement, smaller size and eventually lower cost than conventional 2D packaging. Some of the basic driving forces for 3D integration are

There have been several 3D integration techniques and associated challenges presented in the Wafer Level Packaging and System-in-a-Package fields. The issues specifically related to Through Silicon Via (TSV) are presented in tables derived from The International Technology Roadmap for Semiconductors.

The Holy Grail of 3D IC integration

3D Integrated Circuit with wafer level packaging where all the chips [e.g., microdisplay, MEMS, memory, microprocessor, multiple outputs dc-dc converter, digital
signal processor, microbattery, and analog-to-digital (A/D) mixed signal] are stacking in three dimensions. Just as with many other new technologies, 3D IC integration still faces many critical issues. There are still many challenges in the development of 3D IC integration, some of them being:
• Design guidelines and software are not available.
• Test methods and equipment are lacking.
• Known good dies (KGDs) are required.
• Through-silicon vias (TSVs) with redistribution layers (RDLs)
usually are required.
• Microbumps usually are required.
• Equipment accuracy is necessary for alignments.
• Fast chips must be mixed with slow chips.
• Large chips must be mixed with small chips.
• Wafer thinning and thin-wafer handling during processing
are necessary.
• Thermal issues:
• The heat flux generated by stacked multifunctional chips
in miniature packages is extremely high.
• 3D circuits increase total power generated per unit surface
area.
• Chips in the 3D stack may be overheated if proper and
adequate cooling is not provided.
• The space between the 3D stack may be too small for cooling
channels (i.e., no gap for fluid flow).
• Thin chips may create extreme conditions for on-chip hot
spots.
• 3D IC stacking inspection methodology is needed.
• 3D IC stacking expertise is lacking.
• 3D IC stacking infrastructure is lacking.
• 3D IC stacking standards are lacking.

In the past few years, some of these critical issues have been studied by a number of experts. Their results have already been disclosed in diverse journals or, more specifically, in the proceedings of many conferences, symposia, and workshops whose primary emphases have been on electrical packaging and interconnection. Consequently, there is no single source of information devoted to the state of the art of 3D IC integration with WLP technology

Moore’s Law versus More Than Moore (MTM)

In April 1965, Moore published a paper in Electronics with the title, “Cramming More Components onto Integrated Circuits.” Based on a few data points, Moore proposed to put more transistors on an IC by reducing the feature sizes. Further, he suggested that the number of transistors on an IC (for minimum cost) doubles every 24 months. In the past 40+ years, Moore’s observation (law) about silicon integration (i.e., cost, yield, and reliability) has been the most powerful driver for development of the microelectronics industry. This law places emphasis on lithography scaling and integration [in two dimensions (2D)] of all functions on a




single chip, perhaps through system-on-chip (SoC) capabilities. Today, 32-nm ICs are in volume production, and production of 28-nm ICs is planned to begin in the second half of 2010. In the meantime, 22-nm technology has been working/performing very well in research institutions and laboratories.
On the other hand, integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration and WLP, which is called more than Moore (MTM).It should be pointed out that MTM is much more than just SiP.
Based on the silicon-platform technology, anything that involves the integration of electronics, photonics, mechanics, chemistry, heat, magnetics, biology, etc., for functionality and system performance when interacting with people and the environment can be called MTM. One of the reasons why MEMS is called MTM is because the microelectronic ICs are thought of as the “brains” of a system, and MEMS augments this decision-making capability with “eyes” and “arms” to allow microsystems to sense and control the environment.

Wednesday, April 13, 2011

Heat Generation in Semi-Conductors

With increasing complexity of semiconductor devices the need for accurate simulations increases as well. Iso-Thermal device simulations in one, two, and three dimensions are performed routinely and the physical models entering such simulations are constantly improved and also extended to new materials. The interest in non-isothermal simulations, however, has been considerably lower,despite the fact that heat generation and dissipation in for instance power devices are certainly not negligible effects. As both the power handling capability of power electronic devices and the number of very large scale integration (VLSI) components on a single chip increase, the interest in device heating and in how to reduce it is expected to become progressively larger.

Modeling Heat Generation in a Semi-Conductor Device

It is well known that for an electrolyte solution Gibbs equation is given by

$\ d U^o = TdS - PdV+ \sum_{i} \mu^{(0)}dN_i$

where $\ U^o$ is the internal energy in the absence of an externally applied potential, T is the absolute temperature, S is the entropy, P the pressure, $\ N_i$ the number of ions of the ith species in volume V, and , $\mu_{0} is the electrochemical potential of the ith species, containing a contribution from the electrostatic potential of the ions. Of course, this relation can equally well be applied to semiconductors with “ions” replaced by electrons (i=e and holes (i=h).

Since $\ U^o$ is a homogeneous function of S, V, and $\ N_i$ Euler’s theorem on homogeneous functions implies
$\ U^o = TS - PV + \sum_{i} \mu^{(0)}dN_i$

leading to the Gibbs-Duhem relation
$\ SdT - Vdp + \sum_{i} d\mu^{(0)}N_i$ = 0
Using lower-case letters to denote densities of extensive variables ($\ u^0$= U^0/V$, etc.), we have
$\ u^o = Ts - P + \sum_{i} \mu^{(0)}dN_i$
$\ sdT - dp + \sum_{i} \mu^{(0)}n_i$ = 0
whereby
$\ du^o = Tds - P + \sum_{i} \mu^{(0)}dn_i$

We are, however, concerned with the transfer of particles between phases, and in this case we must include in the change in energy the work done by the (possibly time varying) external potential as the particles are transferred. The internal energy at the phase located at r is
$\ u= u^0 + \phi\sum_{i}q_in_i$,
where $\ q_i$ is the charge of the ith species. Here $\phi$=$\phi(r,t)$ represents the extra potential felt by a charged particle at phase r due to the presence of a possibly time-varying external potential.
Thus we deduce
$\frac{\partial u}{\partial t} = T\frac{\partial s}{\partial t} + \sum_{i} \mu_{i}\frac{\partial n_i}{\partial t} + \frac{\partial \phi}{\partial t}\sum_{i}q_in_i$

where $\mu_i = \mu^{(0)}_i + q_i\phi_i$

is the total electrochemical potential including the effects of an external field. Since time variations in both the potential contribution \phi in the above equation and in the potential \psi are exclusively due to the application of a time varying
external field, we infer that
$\frac{\partial \phi}{\partial t} = \frac{\partial \psi}{\partial t}$

in each phase. With a notation more appropriate for semiconductors,
$\frac{\partial u_n}{\partial t} + \frac{\partial u_p}{\partial t}= T\frac{\partial s}{\partial t} + \mu^{(n)}\frac{\partial n}{\partial t} + \mu^{(p)}\frac{\partial p}{\partial t} + q(n - p)\frac{\partial \psi}{\partial t}$ --(1)

To evaluate the time derivative of the entropy density s we choose to express s as a function of T, n, and p:

$\ ds = \left(\frac{\partial s}{\partial T} \right)_{n,p}dT + \left(\frac{\partial s}{\partial n} \right)_{T,p}dn + \left(\frac{\partial s}{\partial p} \right)_{T,n}dp$

Furthermore, the specific heat of the electron-hole subsystem at constant volume, $\ c^{(e,h)}_v$, is given by
$\ c^{(e,h)}_v = T\left(\frac{\partial s}{\partial T} \right)_{n,p}$

Using the Maxwell"s_equations

$\left(\frac{\partial s}{\partial T} \right)_{T,p} = - \left(\frac{\partial \mu^{(n)}}{\partial T} \right)_{n,p} and \left(\frac{\partial s}{\partial p} \right)_{T,n} = - \left(\frac{\partial \mu^{(p)}}{\partial T} \right)_{n,p}$

adding this to (1) and also considering the contribution of phonon energy,
$\left(\frac{\partial u_L}{\partial t} \right)= c^{(L)}_v\left(\frac{\partial T}{\partial t} \right)$
we get
$\frac{\partial u}{\partial t} = c_v\frac{\partial T}{\partial t} - q\left(\phi_n - T\left(\frac{\partial \phi_n}{\partial T} \right)_{n,p} \right)\frac{\partial n}{\partial t} + q\left(\phi_p - T\left(\frac{\partial \phi_p}{\partial T} \right)_{n,p} \right)\frac{\partial p}{\partial t} + q(p - n)\frac{\partial \psi}{\partial t}$

where $\ c = c^{(eh)}_v + c^{(L)}_v$

When applied to the electron-hole subsystem, the phenomenological equation of Irreversible Thermodynamics state that
$\ J^n = L^{nn}\bigtriangledown\left( - \frac{ \mu^{(n)}}{T} \right) +L^{np}\bigtriangledown\left( - \frac{ \mu^{(p)}}{T} \right) + L^{nu}\bigtriangledown\left(\frac{ 1 }{T} \right)$

$\ J^p = L^{pn}\bigtriangledown\left( - \frac{ \mu^{(n)}}{T} \right) +L^{pp}\bigtriangledown\left( - \frac{ \mu^{(p)}}{T} \right) + L^{pu}\bigtriangledown\left(\frac{ 1 }{T} \right)$

$\ J^u_{eh} = L^{un}\bigtriangledown\left( - \frac{ \mu^{(n)}}{T} \right) +L^{up}\bigtriangledown\left( - \frac{ \mu^{(p)}}{T} \right) + L^{uu}\bigtriangledown\left(\frac{ 1 }{T} \right)$

In absence of a magnetic field, the Onsager relations state that

$\ L^{\alpha\beta} = (L^{\beta\alpha})^T, \alpha, \beta = n,p,u$
If we restrict attention to cubic crystals, in which case the transport tensors are diagonal with identical diagonal elements, the Onsager relations become particularly simple, introducing introduce transport coefficients.

$\ J_n = -qn\mu_n\bigtriangledown\phi_n + \sigma_{np}\bigtriangledown\phi_p + qnD^T_n\bigtriangledown T$
$\ J_p = \sigma_{np}\bigtriangledown\phi_n - qp\mu_p\bigtriangledown\phi_p + qnD^T_p\bigtriangledown T$
$\ J^Q_{(eh)} = qnD^T_nT\bigtriangledown\phi_n - qpD^T_pT\bigtriangledown\phi_p - \lambda^Q\bigtriangledown T$
where
$\mu_n = electron mobility$
$\mu_h = hole mobility$
$\sigma_np = transport coefficient$
Also the electrical current densities
$\ J_n = -qJ^n and J_p = qJ^p$
and also changed and also changed from $\ J^u_{eh}$ to the heat current density $\ J^Q_{eh}$ in order to preserve some of the symmetry in the matrix of transport coefficients. The two current densities are related according to
$\ J^Q_{eh} = J^u_{eh} - \phi_nJ_n - \phi_pJ_p$
In conventional simulation of semiconductor devices,based on the drift-diffusion model, the transport coefficient $\sigma_np $ is zero.
It is possible to express $\ J^Q_{eh}$, in terms of $\ J_n, J_p, and \bigtriangledownT $. It can now be show that
$\ J^Q_{eh} = - \Pi_n J_n + \Pi_p J_p - \kappa_{eh}\bigtriangledownT$

where
$\Pi_n = \frac{1}{1 - \theta}\left(\Pi^o_n - \theta_n\Pi^o_p)$,

$\Pi_p = \frac{1}{1 - \theta}\left(\Pi^o_p - \theta_p\Pi^o_n)$,

$\theta_n = \frac{\sigma_{np}}{qn\mu_n}$, $\theta_p = \frac{\sigma_{np}}{qn\mu_p}$

$\theta = \theta_n\theta_p$

$\Pi^0_n = T\frac{D^T_n}{\mu_n}, \Pi^0_p = T\frac{D^T_p}{\mu_p}$

$\kappa_{eh} = \frac{1}{1-\theta}\left(\kappa^0_{eh} + \frac{2}{T}\sigma_{np}\Pi^0_n\Pi^0_p -\theta\lambda^Q )$
The quantities with a zero superscript are the values of the corresponding quantities in the approximation $\sigma_np=O$, i.e., when we neglect electron-hole scattering in the non-diagonal transport coefficients.

Combining the expressions for $\ J^Q_{eh}$ and adding contribution from lattice we obtain
$\ J^u = - \left(\Pi_n - \phi_n)J_n + \left(\Pi_p + \phi_p)J_p -\kappa\bigtriangledown T $
where
$\kappa = \kappa_{eh} = \kappa_L $
is the thermal conductivity. The transport coefficients $\Pi_n$ and $\Pi_p$ are the Peltier coefficients and quantify the idea that the particles in a particle current also carry energy.
Substituting (1) in the adove equation we get
$\ c_v \frac{\partial T}{\partial t} + \bigtriangledown T \left( - \kappa \bigtriangledown T) = H$
where the heat generation term is
$\ H = \bigtriangledown \left( \left(\Pi_n - \phi_n \right)J_n - \left(\Pi_p + \phi_p \right)J_p \right)+ q\left( \phi_n - T \left(\frac{\partial \phi_n}{\partial T}\right)_{n,p} \right)\times \frac{\partial n}{ \partial t} - q\left( \phi_p - T \left(\frac{\partial \phi_p}{\partial T}\right)_{n,p} \right)\frac{\partial p}{\partial t}$
This is valid for cubic crystals with a position-dependent band structure of any complexity in a generalized drift-diffusion approximation and with Fermi-Dirac statistics. By using the continuity equations, other forms of H, not containing explicit time derivatives of n and p, are possible.

Monday, April 11, 2011

Micro Electric Mechanical Systems Why a career choice ?

The MEMS market forecast by Yole Development calls for $10 billion by 2010 and $14 billion by 2012. [For 2008, Jean Christophe Eloy, CEO of Yole, expects the market to be $7.8 billion. This represents a combined annual growth rate (CAGR) of 14 percent for the 2007–2012 period. The packaging cost of a MEMS product in general is between 60 and 80 percent. Thus MEMS packaging could be a $7 billion market by 2010 and $10 billion by 2012.

The MEMS devices that make up the market forecast are, for example, inkjet (IJ) heads, pressure sensors, silicon microphones, accelerometers, gyroscopes, MOEMS devices, microbolometers, microdisplays, microfluidics, radiofrequency (RF) MEMS, microtips, microfuel cells, and emerging MEMS. These MEMS devices can be applied to the automotive, aeronautics, consumer, defense, industrial, medical, life science, and telecommunication industries. Their units and market values have been provided by Yole Development and are
shown, which also include the forecasts up to 2012. It can be seen that the value of MEMS production is expected to double in 2012 (from 2007) and that the total units of MEMS production
are expected to quadruple in 2012 (from 2007).

MEMS value market forecast for 2006–2012 ($ US millions).
According to Jean Christophe Eloy, whose company tracks 150 MEMS applications, RF MEMS is expected to have the highest growth (50 percent), followed by microfluidic chips for drug delivery (42 percent), silicon microphones (32 percent), microfluidic chips for diagnostics (23 percent), microtips and microprobes (22 percent), and microbolometers (20 percent). Eloy also said that the most promising MEMS devices include accelerometers for humanmachine interfaces, with a CAGR exceeding 120 percent, followed by RF-MEMS devices for automatic test equipment (81 percent).
MEMS volume market forecast for 2006–2012 (millions of units).

SMT Design, Assembly, and Test

The IPC has defined three general end-product classes of electronic products.
• Class 1: General consumer products
• Class 2: Dedicated service electronic products—including communications, business, instrumentation,
and military products, where high performance and extended life are required, and where
uninterrupted service is desired but not critical.
• Class 3: High reliability electronic products—commercial and military products where equipment
downtime cannot be tolerated.

All three performance classes have the same needs with regard to necessary design and process functions.

  1. Circuit design (not covered in this handbook)
  2. Thermal design considerations
  3. Substrate [typically, printed circuit board (PCB) design
  4. Bare PCB fabrication and test
  5. Application of solder paste
  6. Placement of components in solder paste
  7. Reflowing of solder paste
  8. Cleaning, if necessary
  9. Testing of populated PCB 
Once the circuit design is complete, substrate design and fabrication, most commonly of a printed circuit board (PCB), enter the process. Generally, PCB assemblies are classified into types and classes as described in IPC’s “Guidelines for Printed Board Component Mounting,” IPC-CM-770. It is unfortunate that the IPC chose to use the term class for both end-product classification and for this definition. The reader of this and other documents should be careful to understand which class is being referenced. The types are as follows:
  1. Type 1: components (SMT and/or THT) mounted on only one side of the board
  2. Type 2: components (SMT and/or THT) mounted on both sides of the board
The types are further subdivided by the types of components mounted on the board.
• A: through-hole components only
• B: surface mounted components only
• C: simple through-hole and surface mount components mixed
• X: through-hole and/or complex surface mount components, including fine pitch and BGAs
• Y: through-hole and/or complex surface mount components, including ultrafine pitch and chip
scale packages (CSPs)
• Z: through-hole and/or complex surface mount, including ultrafine pitch, chip on board (COB),
flip chip, and tape automated bonding (TAB)

The most common type combinations, and the appropriate soldering technique(s) for each, are
• 1A: THT on one side, all components inserted from top side
Wave soldering
• 1B: SMD on one side, all components placed on top side
Reflow soldering
• 1C: THT and SMD on top side only
Reflow for SMDs and wave soldering for THTs
• 2B: SMD on top and bottom
Reflow soldering
• 2C/a: THT on top side, SMD on bottom side
Wave soldering for both THTs and bottom-side SMDs
• 2C/a: THT (if present) on top side, SMD on top and bottom
Reflow and wave soldering (if THTs are present)
• 1X: THT (if present) on top side, complex SMD on top
Reflow and wave soldering (if THTs are present)
• 2X/a: THT (if present) on top side, SMD/fine pitch/BGA on top and bottom
Reflow and wave soldering (if THTs are present)
• 2Y, 2Z: THT (if present) on top side, SMD/ultrafine pitch/COB/flip chip/TAB on top and bottom
Reflow and wave soldering (if THTs are present)

The “/a” refers to the possible need to deposit adhesive prior to placing the bottom-side SMDs. If THTs are present, bottom-side SMDs will be placed in adhesive, and both the bottom-side SMDs and the protruding THT leads will be soldered by passing the assembly through a dual-wave soldering oven. If THTs are not present, the bottom-side SMDs may or may not be placed in adhesive. The surface tension of molten solder is sufficient to hold bottom-side components in place during top-side reflow. 

A Type 1B (top side SMT) bare board will first have solder paste applied to the component pads on the board. Once solder paste has been deposited, active and passive parts are placed in the paste. For prototype and low-volume lines, this can be done with manually guided x-y tables using vacuum needles to hold the components, whereas, in medium- and high-volume lines, automated placement equipment is used. This equipment will pick parts from reels, tubes, or trays and then place the components at the appropriate pad locations on the board, hence the term pick-and-place equipment.

After all parts are placed in the solder paste, the entire assembly enters a reflow oven to raise the temperature of the assembly high enough to reflow the solder paste and create acceptable solder joints at the component lead/pad transitions. Reflow ovens most commonly use convection and IR heat sources to heat the assembly above the point of solder liquidus, which for 63/37 tin-lead eutectic solder is 183° C. Due to the much higher thermal conductivity of the solder paste compared to the IC body, reflow soldering temperatures are reached at the leads/pads before the IC chip itself reaches damaging temperatures.


For a Type 2B (top and bottom SMT), the board is inverted and the process repeated. If mixed-technology Type 2C (SMD only on bottom) is being produced, the board will be inverted, an adhesive will be dispensed at the centroid of each SMD, parts will be placed, the adhesive will be cured, the assembly will be re-righted, through-hole components will be mounted, and the circuit assembly will then be wave soldered, which will create acceptable solder joints for both the through-hole components and bottom-side SMDs. It must be noted that successful wave soldering of SMDs requires a dual-wave machine with one turbulent wave and one laminar wave. For any of the type assemblies that have THT on top side and SMDs (including SMT, fine pitch, ultrafine pitch, BGA, flip chip, etc.) top and bottom, the board will first be inverted, adhesive dispensed, SMDs placed on the bottom-side of the board, the adhesive cured, the board re-righted, through-hole components placed, and the entire assembly wave soldered. It is imperative to note that only passive components and small active SMDs can be successfully bottom-side wave soldered without considerable experience on the part of the design team and the board assembly facility. It must again be noted that successful wave soldering of SMDs requires a dual-wave machine with one turbulent wave and one laminar wave. The board will then be turned upright, solder paste deposited, the top-side SMDs placed, and the assembly reflow soldered. It is common for a manufacturer of through-hole boards to convert first to a Type 2C (SMD bottom side only) substrate design before going to an all-SMD Type I design. Since this type of board requires only wave soldering, it allows amortization of through-hole insertion and wave soldering. Many factors contribute to the reality that most boards are mixed-technology boards. While most components are available in SMT packages, through-hole connectors may still be commonly used for the additional  strength that the through-hole soldering process provides, and high-power devices such as three-terminal regulators are still commonly through-hole due to off-board heat-sinking demands. Both of these issues are actively being addressed by manufacturers and solutions exist that allow all-SMT boards with connectors and power devices.

Again, it is imperative that all members of the design, build, and test teams be involved from the design stage. Today’s complex board designs mean that it is entirely possible to exceed the ability to adequately test a board if test is not designed in, or to robustly manufacture a the board if in-line inspections and handling are not adequately considered. Robustness of both test and manufacturing are only assured with full involvement of all parties to overall board design and production.

There is an older definition of types of boards that the reader will still commonly find in books and articles, including some up through 1997. For this reason, those three types will be briefly defined here, along with their soldering techniques. The reader is cautioned to be sure which definition of board types is being referred to in other publications. In these board definitions, no distinction is made among the various types of SMDs. That is, SMD could refer to standard SMT, fine-pitch, ultrafine-pitch, BGAs, etc. This older definition was conceived prior to the use of the various chip-on-board and flip chip technologies and does not consider them as special cases.
Type I, II, and III SMT circuit boards.

• Type 1: an all-SMT board, which could be single- or double-sided. Reflow soldering is used and
is one-pass for a single-sided board. For a double-sided board, several common techniques are
used:
– Invert board, deposit adhesive at centroid of parts. Deposit solder paste. Place bottom side
in eutectic paste, cure adhesive, then reflow. Invert board, place top-side parts in eutectic
paste, reflow again.
– Invert board, place bottom-side parts in eutectic paste, reflow. Invert board, place top-side
parts in eutectic paste, reflow again. Rely on the surface tension of the molten solder paste to
keep bottom-side parts in place.
– Invert board, place bottom-side parts in high-temperature paste. Reflow at appropriate high
temperature. Invert board, place top-side components in eutectic paste, reflow again. The
bottom-side paste will not melt in eutectic reflow temperatures.
• Type 2: a mixed-technology board, composed of THT components and SMD components on the
top side. If there are SMD components on the bottom side, a typical process flow will be:
– Invert board, place bottom-side SMDs in adhesive. Cure adhesive.
– Invert board, place top-side SMDs. Reflow board.
– Insert THT parts into top side.
– Wave solder both THT parts and bottom-side SMDs.
Typically, the bottom-side SMDs will only consist of chip devices and SO transistors. Some
publications will also call Type 2 a Type 2A (or Type IIA) board.
• Type 3: a mixed technology board, with SMDs only on the bottom side, and typically only chip
parts and SO transistors. The typical process flow would be:
– Invert board, place bottom-side SMDs in adhesive. Cure adhesive.
– Insert THT parts into top side.
– Wave solder both THT parts and bottom-side SMDs.
Due to this simplified process flow, and the need for only wave soldering, Type 3 boards are an
obvious first step for any board assembler moving from THT to mixed-technology boards. Some
publications will also call Type 3 a Type 2B (or Type IIB) board


Surface mount technology (SMT)

Surface mount technology is a collection of scientific and engineering methods needed to design, build, and test products made with electronic components that mount to the surface of the printed circuit board without holes for leads. This definition notes the breadth of topics necessary to understand SMT and also clearly says that the successful implementation of SMT will require the use of concurrent engineering. Concurrent engineering, means that a team of design, manufacturing, test, and marketing people will concern themselves with board layout, parts and part placement issues, soldering, cleaning, test, rework, and packaging—before any product is made.

Considerations in the Implementation of SMT

The main reasons to consider implementation of SMT include
• reduction in circuit board size
• reduction in circuit board weight
• reduction in number of layers in the circuit board
• reduction in trace lengths on the circuit board, with correspondingly shorter signal transit times
and potentially higher-speed operation
• reduction in board assembly cost through automation

However, not all of these reductions may occur in any given product redesign from through-hole technology (THT) to SMT. Obviously, many current products, such as digital watches, laptop computers, and camcorders, would not be possible without the size and cost advantages of SMT. Important in all electronic products are both quality and reliability.
• Quality = the ability of the product to function to its specifications at the conclusion of the assembly process.
• Reliability = the ability of the product to function to its specifications during its designed lifetime.
Most companies that have not converted to SMT are considering doing so. All, of course, is not golden in SMT Land. During the assembly of a through-hole board, either the component leads go through the holes or they don’t, and the component placement machines typically can detect the difference in force involved and yell for help. During SMT board assembly, the placement machine does not have such direct feedback, and accuracy of final soldered placement becomes a stochastic (probability-based) process, dependent on such items as component pad design, accuracy of the PCB artwork and fabrication (which affects the accuracy of trace location), accuracy of solder paste deposition location and deposition volume, accuracy of adhesive deposition location and volume if adhesive is used, accuracy of placement machine vision system(s), variations in component sizes from the assumed sizes, and thermal issues in the solder reflow process. In THT test, there is a through-hole at every potential test point, making it easy to align a bed-of-nails tester. In SMT designs, there are not holes corresponding to every device lead. The design team must consider form, fit and function, time-to-market, existing capabilities, testing, rework capabilities, and the cost and time to characterize a new process when deciding on a change of technologies.

Wafer-Bonding Technologies for Packaging

Wafer bonding is used widely in MEMS fabrication and packaging. It refers to approaches of firmly joining two wafers (or more) to create a stacked and bonded wafer. There are three main kinds of waferbonding processes: direct bonding, field-assisted bonding, and bonding with an intermediate layer. The choice of which is most suitable depends on the particular application and the materials involved. Silicon-to-silicon direct bonding, also called fusion bonding, is a direct silicon-to-silicon bonding technique without the assistance of significant pressure or any intermediate layers or fields. The process requires rather flat and clean surfaces as the bonding interface for the two wafers. The surfaces of silicon wafers are cleaned and rinsed first. Hydroxyl (–OH) groups form on the surfaces of the two wafers with a thin native silicon oxide layer (i.e., hydrophilic surface). Two wafers can be joined together at room temperature, resulting in an immediate weak bond owing to van der Waals forces. Then the bonded wafers are heated to 800 to 1000°C to remove the water molecules and leave behind Si–O–Si bonds at the interface. Owing to perfectly matched thermal-expansion coefficients of the two wafers, silicon direct-bonded wafers have little or no residual stress owing to thermal mismatch. However, silicon direct bonding normally is used as the beginning step in an integrated process because of the rather high annealing temperature and high-quality requirement of the bonding interface in terms of cleanness and flatness.


Package Design

Pin grid arrays
Larger chips, with more leads, have outgrown the DIP configuration. The pin grid array is a package designed for larger chips. It features a pre made “sandwich” with the outer leads coming out of the bottom of the package in the form of pins. The chip is attached in a cavity that is formed in either the top or bottom of the body, usually using bump/flip-chip technology. Connections to the chip cover the entire chip area, unlike most chips with connections restricted to bonding pads around the periphery of the chip. Ceramic PGAs are hermetically sealed with a soldered metal lid.


Ball grid arrays (BGAs) or flip-chip ball grid arrays (FCBGAs)
BGAs have the same body shape as PGAs. Instead of pins on the package bottom, there is a series of solder bumps (balls) used to connect the package to the PCB. This is essentially the same technology used to connect die to packages. The effect is to lower the package profile and weight as well as providing higher pin counts by using the whole chip surface for bonding pads. Balls (or bumps) also bring the aspect absorbing stresses created from the thermal expansion differences between the package and the PCB.

A simple Ball Grid Array

Quad packages
While pin grid array packs are a convenient design for larger chips, their ceramic construction is expensive compared to molded epoxy packages. This consideration led to the development of the “quad” package. A quad (short for quadrant) pack is constructed by the epoxy molded technique but has leads coming out of all four sides of the package.
Thin packages
New products such as smart cards require thin packages. Several techniques are used to make thinner packages. They are called flat packs (FPs), thin small outline packages (TSOPs), small outline IC (SOIC), or ultra-thin packages (UTPs). Flat packs are constructed by the same techniques used to form DIP packages. These packages are designed with flatter height profiles and have their leads bent out to the side of the package. Ultra-thin packages have total body heights in the 1 mm range. There are also quad flat packs (QFPs).

Chip-scale packages

In the world of ICs, the perfect package is no package. It is recognized that any package brings with it electrical resistance, weight, the opportunity to degrade the circuit performance, and cost. Overall, the smaller the package, the cheaper the cost of packaging and the benefit of higher densities. Chip-scale packages meet this need. They are simply packages with dimensions within 1.2 times the die size. The challenges are to provide adequate mechanical and environmental protection for easy connection to printed circuit boards. General design approaches favor flip-chip technology with ball grid arrays and blob top protection. The march to smaller packages and more reliable electrical connections has lead to the micro-ball grid array, or μBGA.

Multichip modules (MCMs)
Mounting individual chip packages on a PCB presents several problems. A chip package is several times the area of the chip taking up space on the board. Circuit resistance is increased by the individual resistances of all the package pins, and the electrical path lengths are multiplied by the number of chips and package leads. Each of these problems is reduced by mounting several chips on the same substrate. The technology is similar to hybrid circuits, but thick film screened components are not, or rarely, used. Three types of MCMs have evolved. MCM-L (laminated) is similar to advanced laminated printed circuit boards, using copper foil conductors on plastic dielectrics. MCM-C (ceramic) are more like hybrid circuits. The substrate is a cofired ceramic with thick film conductors. MCM-D (deposited) uses ceramic, metal, or silicon substrates use deposited thin metal conductors.

Packaging Processes

Prepackaging wafer preparation
After the final passivation layer and an alloy step in wafer fabrication, the circuits are complete. However, one or two additional processes may be performed on the wafer before transfer to packaging. These steps (wafer thinning and backside gold) are optional, depending on the wafer thickness and the particular circuit design.

Wafer thinning.
The trend to thicker wafers presents several problems in the packaging process. Thicker wafers require the more expensive complete saw-through method at die separation. While sawing produces a higher-quality die edge, the process is more expensive in time and consumption of diamond-tipped saws. Thicker die also require deeper die attach cavities, resulting in a more expensive package. Both of these undesirable results are avoided by thinning the wafers before die separation. Another situation requiring wafer thinning is electrical in nature. If the wafer backs are not protected as the wafers go through the dopant operations in fabrication, the dopants will form electrical junctions in the wafer back, which may interfere with good conduction in the back contact that is required for the circuit to operate correctly. These junctions may require physical removal by wafer thinning. The thinning step generally takes place between wafer sort and die separation. Wafers are reduced to a thickness of 0.2 to 0.5 mm.
Thinningis done by the same processes (mechanical grinding and chemical-mechanical polishing-CMP) used to grind wafers in the wafer preparation stage. An alternate method is to protect the front of the wafers and chemically etch material from the back. Wafer thinning is a worrisome process. In back grinding, there is the concern of scratching the front of the wafer and of wafer breakage. Since the wafer must be held down on the grinder or polishing surface, the front of the wafer must be protected and, once thinned, wafers are easier to break. In back etching, there is a similar need to protect the front of the wafer from the etchant. The protection can be provided by spinning a thick layer of photoresist on the front side. Other methods include attaching adhesive-backed polymer sheets cut to the wafer diameter. Stresses induced in the wafer by grinding/polishing processes must be controlled to prevent wafer and die warping. Wafer warping interferes with the die separation process (broken and cracked die). Die warping creates die attach problems in the packaging process.

Backside gold.
Another optional wafer process is adding a layer of backside gold. A layer of gold is required on wafers that are going to be Packaging attached to the package by eutectic techniques. The gold is usually applied in the fabrication area (after back grinding) by evaporation or sputtering. 

Die separation
The chip-packaging process starts with the separation of the wafer into individual dies. The two methods of die separation are scribing and sawing 
 
Scribing.
Scribing, or diamond scribing, was the first production die separation technique developed in the industry. It requires dragging a diamond-tipped scribe through the center of the scribe lines and separating the die by flexing the wafer. Scribing becomes unreliable in wafers over 10 mils thick.
 
Sawing.
The advent of thicker wafers has led to the development of sawing as the preferred die separation method. A saw consists of a wafer table with rotation capability, a manual or automatic vision system for orienting the scribe lines, and a diamond-impregnated round saw. Two techniques are used. Both start with the passage of the diamond saw over the scribe lines. For thinner wafers, the saw is lowered into the wafer surface to create a trench about one-third of the way through the wafer. The separation of the wafer into die is completed by the stress and roller technique used in the scribing method. The second sawing method is to separate the die by a complete saw through of the wafer. Often, the wafers for complete saw-through are first mounted on a flexible plastic film. The film holds the die in place after the sawing operation and aids the die pick operation. Sawing is the preferred die separation method due to the cleaner die edges and the fewer cracks and chips left on the sides of the die.

Die pick and place
After sawing, the separated die are transferred to a station for selection of the functioning die (non-inked). In the manual method, an operator will pick up each of the non-inked dies with a vacuum wand and place it in a sectioned plate. Wafers that come to the station on the flexible film are first placed on a frame that stretches the film. The stretching separates the die, which aids the die pick operation. In the automated version of this operation, a memory tape or disk that has the locations of the good die (from wafer sort) is loaded into the tool. A vacuum wand picks up good die and automatically places them in a sectioned plate for transfer to the next operation.
 
Die inspection
Before being committed to the rest of the process, the die are given an optical inspection. Of primary interest is the quality of the die edge, which should be free of chips and cracks. This inspection also sorts out surface irregularities, such as scratches and contamination. Inspection may be manual with microscopes or automated with a vision system. At this step, the die is ready to go into a package.
 
Die attach
Die attachment has several goals: to create a strong physical bond between the chip and the package, to provide either an electrical conducting or insulating contact between the die and the package, and to serve as a medium to transfer heat from the chip to the package. A requirement is the permanency of the die-attachment bond. The bond should not loosen or deteriorate during subsequent processing steps or when the package is in use in an electronic product. This requirement is especially important for packages that will be subjected to high physical forces, such as in rockets. Additionally, the die attach materials should be contaminant-free and should not outgas during subsequent process heating steps. Lastly, the process itself should be productive and economical.
 
Eutectic die attach.
There are two principal methods of die attach: eutectic and epoxy adhesives. The eutectic method is named for the phenomenon that takes place when two materials melt together (alloy) at a much lower temperature than either of them separately. For die attach, the two eutectic materials are gold and silicon. Gold melts at 1063°C, while silicon melts at 1415°C. When the two are mixed together, they start alloying at about 380°C. Gold is plated onto the die-attach area and alloys with the bottom of the silicon die when heated. The gold for the die-attach layer is actually a sandwich. The bottom of the die-attach area is deposited or plated with a layer of gold. Sometimes, a preformed piece of metal composed of a gold and silicon mixture is placed in the die-attach area. When heated, these two layers, along with a thin layer of silicon from the wafer back, form a thin alloy layer. This layer is the actual bond forming the die-package attachment. Eutectic die attach requires four actions. First is the heating of the package until the gold-silicon forms a liquid. Second is the placement of the chip on the die-attach area. Third is an abrasive action, called scrubbing , that forces the die and package surfaces together. It is this action, in the presence of the heat, that forms the gold-silicon eutectic layer. The fourth and final action is the cooling of the system, which completes the physical and electrical attachment of the chip and package. Eutectic die attach can be performed manually or by an automated machine that performs the four actions. Gold-silicon eutectic die attach is favored for high-reliability devices and circuits for its strong bonds, heat dissipation properties, thermal stability, and lack of impurities. 
 
Epoxy die attach.
The alternate die-attach process uses thick liquid epoxy adhesives. These adhesives can form an insulating barrier between the chip and package or become electrically and heat conductive with the addition of metals such as gold or silver. Polyimide may also be used as an adhesive. Popular adhesives are silver-filled epoxy for copper lead frames and silver-filled polyimide for Alloy 22 metal frames. The epoxy process starts with the deposit of the epoxy adhesive in the die-attach area by dispensing the adhesive with a needle or screen printing it into the die-attach area. The die, held by a vacuum wand, is positioned in the center of the die-attach area. The second action is to force the die into the epoxy to form a thin uniform layer under the die. The final action is a curing step in an oven at an elevated temperature that sets the epoxy bond. Epoxy die attach is favored for its economy and ease of processing, in that the package does not have to be heated on a stage. This factor makes the automation of the process easier. When compared to goldsilicon eutectic die attach, epoxy has the disadvantage of potential decomposition at the high temperatures of bonding and sealing operations. Epoxy die-attach films also do not have the bonding power of the eutectics. Regardless of the attachment method used, there are several marks of a successful die attach. One is the proper and consistent alignment of the die in the die-attach area. Proper placement pays off in faster and higher-yield automatic bonding. Another desired result is a solid, uniform, and void-free contact over the entire area of the chip. This is necessary for mechanical strength and good thermal conduction. One evidence of a uniform bond is a continuous joint or “fillet” between the die edge and the package. The final mark of a good die-attach process is a die-attach area free of flakes or lumps that can come loose during use and cause a malfunction. 
 
Die-to-package bonding
Once the die and package are attached, they go to the bonding process. This is perhaps the most critical of all the assembly operations. Three techniques provide the critical chip/package connection: wire bonding, bump/flip-chip, and TAB. In wire bonding, up to hundreds of wires must be perfectly bonded from the bonding pads to the package inner leads. In bump/flip chip, the bonding pad/package connection is a solder ball. Tape automated bonding (TAB) system is a process that bonds the lead frame leads directly to the die bonding pads in one step. 
 
Wire bonding
The wire bonding procedure is simple in concept. A thin (0.7 to 1.0 mil) wire is first bonded to the chip bonding pad and spanned to the inner lead of the package lead frame. The third action is to bond the wire to the inner lead. Last, the wire is clipped and the entire process repeated at the next bonding pad. While simple in concept and procedure, wire bonding is critical because of the precise wire placement and electrical contact requirements. In addition to accurate placement, each and every wire must make good electrical contact at both ends, span between the pad and inner lead in a prescribed loop without kinks, and be at a safe distance from neighboring wires. Wire loops in conventional packages are 8 to 12 mils, while those in ultra-thin packages are 4 to 5 mils. Distances between adjacent wires are referred to as the pitch of the bonding. Wire bonding is done with either gold or aluminum wires. Both are highly conductive and ductile enough to withstand deformation during the bonding steps and still remain strong and reliable. Each has its advantages and disadvantages, and each is bonded by different methods. 
 
Gold wire bonding.
Gold has several pluses as a bonding wire material. It is the best known room-temperature conductor and is an excellent heat conductor. It is resistant to oxidation and corrosion, which translates into an ability to be melted to form a strong bond with the aluminum bonding pads without oxidizing during the process. Two methods are used for gold bonding. They are thermocompression and thermosonic.
Thermocompression bonding (also known as TC bonding) starts with the positioning of the package on the bonding chuck and the heating of the chip and package to between 300 and 350°C. Chips that are going to be enclosed in an epoxy molded package are processed through die attach and bonded with the chip on the lead frame only. The bonding wire is fed out of a thin tube called a capillary. An instantaneous electrical spark or small hydrogen flame melts the tip of the wire into a ball and positions the wire over the first bonding pad. The capillary moves downward, forcing the melted ball onto the center of the bonding pad. The effect of the heat (thermal) and the downward pressure (compression) forms a strong alloy bond between the two materials. This type of bonding is often called ball bonding. After the ball bond is complete, the capillary feeds out more wire as it travels to the inner lead. At the inner lead, the capillary again travels downward to where the gold wire is forced by the heat and pressure to melt onto the gold-plated inner lead. The spark or flame then severs the wire, forming the ball for the next pad bond. This procedure is repeated until every pad and its corresponding inner pad are connected.
Thermosonic, gold ball bonding follows the same steps as thermo-compression bonding. However, it can take place at a lower temperature. This benefit is provided by a pulse of ultrasonic energy that is sent through the capillary into the wire. This additional energy is sufficient to provide the heat and friction to form a strong alloy bond. The majority of production gold wire bonding is done on automatic machines that use sophisticated techniques to locate the pads and span the wire to the correct inner lead. The fastest bonding machines can perform thousands of bonds per hour. There are two major drawbacks to the use of gold bonding wires. First is the expense of the gold. Second is an undesirable alloy that can form between the gold and aluminum. This alloy can severely reduce the conduction ability of the bond. It forms a purplish color and is known as the “purple plague.”

Aluminum wire bonding.
Aluminum wire, while not having the conduction and corrosion-resistance properties of gold, is still an important bonding wire material. A primary advantage is its lower cost. The second advantage is that the bond with the aluminum bonding pad is a monometal system and thus less susceptible to corrosion. Also, aluminum bonding can take place at lower temperatures than gold bonding, making it more compatible with the use of epoxy die-attach adhesives. The bonding of the aluminum follows the same major steps as gold wire bonding. However, the method of forming the bond is different. No ball is formed. Instead, after the aluminum wire is positioned over the bonding pad, a wedge forces the wire onto the pad as a pulse of ultrasonic energy is sent down the wedge to form the bond. After the bond is formed, the wire is spanned to the inner lead where another ultrasonic-assisted wedge bond is formed. This type of bonding is known variously as ultrasonic or wedge bonding. After this bond, the wire is cut. At this point in the process, a major difference between the bonding of the two materials occurs. In gold bonding, the capillary moves freely from pad to inner lead, to pad, and so forth, with the package in a fixed position. In aluminum wire bonding, the package must be repositioned for every single bonding step. The repositioning is necessary to line up the pad and inner lead along the direction of travel of the wedge and wire. This requirement places an additional difficulty on the designers of automatic aluminum bonding machines. Nevertheless, most production aluminum bonding is done on high-speed machines.
 
Bump/flip-chip bonding
Wire bonding presents several problems. There are electrical resistances associated with each bond. There are minimum height limits imposed by the required wire loops. There is the chance of electrical performance problems or shorting if the wires come to close to each other. Plus, the wires require an individual bonding step at both the chip bonding pad and at the package lead. Perhaps the biggest problem results from the increasing number of connections (pin count) needed to operate larger circuits. Chip designers simply run out of space to locate the required number of connections around the periphery of the chip. These issues are addressed by replacing wires with a deposited metal bump on each bonding pad. The bumps are also called balls, as in naming packages using bump/flip-chip processes as ball grid arrays (BGAs). This bonding method allows chip design with bonding pads located both along the edge of the die as well as in the interior of the die. These locations place the bump closer to the chip circuitry, increasing signal processing speed. Connection to the package is made when the chip is flipped over and the bump soldered to a corresponding package inner lead on a package or printed circuit board. IBM calls their version of this technology controlled collapse chip connection. This process leaves the die suspended above the package surface. Physical stresses and strains are absorbed by the soft solder bump. Additional stress tolerance is provided by filling the gap with an epoxy filling, called and underfill. Bump connection technology starts in the wafer fabrication process. Wafers are processed through the usual metallization, passivation, and bonding pad patterning processes. The last patterning process leaves an opening in the passivation layer over the bonding pads. A number of process flows are available to form the solder bumps on the bonding pad. The process described below is an example. 

Sputter deposit intermetal stack.
Lead/tin solder balls are the preferred “bump” material. However, an intermetal layer (or stack) is required between the bonding pad and the solder ball to prevent the lead from diffusing into the aluminum pad and to aid adhesion of the solder ball onto the pad. Various metal stacks are used, including chrome-coppergold (Cr-Cu-Au), titanium-nickel (Ti-Ni), and plain copper.

Patterning step of bump location.
A patterning step covers the die surface with resist, leaving openings over the bonding pads and surrounding dielectric. The resist layer is thick enough to accommodate enough solder to form a ball of sufficient volume to provide structural support and lower electrical resistance between the chip and package or substrate. 

Deposit of intermediate layer stack.
The intermetal materials are evaporated or sputtered through the openings on the pad. Deposit lead/tin solder. Deposit of the lead/tin solder can be by electroplating or evaporation. If electroplating is used, a seed layer is deposited before the electroplating. Lead/tin is used to lower the melting point of the solder. Remove resist. The resist is removed, leaving a bump of lead/tin connected
to the bonding pad.

Package Functions and Design

There are four basic functions performed by a semiconductor package. They are to provide:
  1. A substantial lead system
  2. Physical protection
  3. Environmental protection
  4. Heat dissipation
1.Substantial lead system
The primary function of the package is to allow connection of the chip to a circuit board or directly to an electronic product. This connection cannot be made directly, due to the thin and fragile metal system used to interconnect the components on the chip surface.This difference in wiring sizes is the reason why the chip wiring terminates in the larger bonding pads.
2. Physical protection
The second function of the package is the physical protection of the chip from breakage, particulate contamination, and abuse. Physical protection needs vary from low, as in the case of consumer products, to very stringent, as in the case of automobile circuits, space rockets, and military uses. The protection function is accomplished by securing the chip to a die-attachment area and surrounding the chip, wire bonds, and inner package leads with an appropriate enclosure. The size and eventual use of the chip dictate the choice of materials for the enclosure and the design and size of the package.

3. Environmental protection
Environmental protection of the chip from chemicals, moisture, and gases that may interfere with the chip functioning is provided by the package enclosure.

4. Heat dissipation
Every semiconductor chip generates some heat during operation. Some generate large quantities. The package enclosure materials serve to draw the heat away from most chips. Indeed, one of the factors in choosing a package material is its thermal dissipation property. The chips that generate large quantities of heat require additional consideration in the package design. This consideration will influence the size of the package and will often require the addition of metal heat-dissipating fins or blocks on the package.

Micro-Electric Packaging

For use in a circuit or electronic product, chips or Integrated circuits must be separated from the wafer and, in most cases, put in a protective package. They may also be mounted onto the surface of a ceramic substrate as part of a hybrid circuit, put into a large package with other chips as part of a multichip module (MCM), or be connected directly on board a printed circuit, chip-on-board, or direct chip attach (COB or DCA) . All three options share some common processes. The packaging process, in addition to protecting the chip, provides an electrical connection system allowing the chip to be integrated into an electronic system, and it provides environmental protection and heat dissipation. This series of processes is known variously as packaging, assembly, or the back-end process.

In the packaging process, the chips are called dies or dice. Over the years, semiconductor packaging has lagged wafer fabrication in process sophistication and manufacturing demands. The advent of the VLSI/ULSI era in chip density has forced a radical upgrading of chip packaging technology and production automation. Higher-density chips require more input connections (I) and more output connections (O). These are referred to as the I/O count or simply the pin count. The IRTS lists pin count, cost, chip size, thickness, and temperature considerations as the primary physical drivers of packaging technology. As solid-state circuits have found more applications, the need for special package designs has increased. Higher pin counts have led to the adoption of bump/flip chip technology. Size and speed considerations have driven the use of chip scale packages in consumer products, such as cell phones and hand-held products. The harsh environments of space, automotive use, and military applications require special packages, processing, and testing to ensure high reliability in the field. These packages, processes, and tests are referred to as hi-rel. The other chips and packages are referred to as commercial parts. No longer is packaging the stepchild of the semiconductor industry. Many feel that, eventually, packaging will be the limiting factor on the growth of chip size. For the time being, however, much effort is going into new package designs, new material development, and faster and more reliable packaging processes.

The microelectronics package of today plays a significant role enabling silicon chips to meet their performance targets. Key examples of this are:
1. It is a space transformer enabling interconnect scaling and hence electrical connectivity between the silicon and the motherboard. The figure below shows the typical dimensional transitions enabled between the silicon chip and the package to allow nano-meter sized silicon devices to connect to a motherboard in a computer.

2. It is a key link in the delivery of power to the silicon chip and for the removal of heat generated by the silicon.
3. A well designed package enables high speed signaling in the computing system by minimizing reductions in signal integrity.
4. Packaging protects fragile silicon chips from environmental damage