Wednesday, May 4, 2011

Intel 22nm 3-D Tri-Gate Transistor Technology



The vertical fins of Intel’s revolutionary tri-gate transistors passing through the gates.


New Transistors for 22 Nanometer Chips Have an Unprecedented Combination of Power Savings and Performance Gains

NEWS HIGHLIGHTS

* Intel announces a major technical breakthrough and historic innovation in microprocessors: the world's first 3-D transistors, called Tri-Gate, in a production technology.
* The transition to 3-D Tri-Gate transistors sustains the pace of technology advancement, fueling Moore's Law for years to come.
* An unprecedented combination of performance improvement and power reduction to enable new innovations across a range of future 22nm-based devices from the smallest handhelds to powerful cloud-based servers.
* Intel demonstrates a 22nm microprocessor – codenamed "Ivy Bridge" – that will be the first high-volume chip to use 3-D Tri-Gate transistors.

An illustration of a 32nm transistor compared to a 22nm transistor. On the left side is the 32nm planar transistor in which the current (represented by the yellow dots) flows in a plane underneath the gate. On the right is the 22nm 3-D Tri-Gate transistor with current flowing on 3 sides of a vertical fin.


SANTA CLARA, Calif., May 4, 2011 – Intel Corporation today announced a significant breakthrough in the evolution of the transistor, the microscopic building block of modern electronics. For the first time since the invention of silicon transistors over 50 years ago, transistors using a three-dimensional structure will be put into high-volume manufacturing. Intel will introduce a revolutionary 3-D transistor design called Tri-Gate, first disclosed by Intel in 2002, into high-volume manufacturing at the 22-nanometer (nm) node in an Intel chip codenamed "Ivy Bridge." A nanometer is one-billionth of a meter.


The three-dimensional Tri-Gate transistors represent a fundamental departure from the two-dimensional planar transistor structure that has powered not only all computers, mobile phones and consumer electronics to-date, but also the electronic controls within cars, spacecraft, household appliances, medical devices and virtually thousands of other everyday devices for decades.


"Intel's scientists and engineers have once again reinvented the transistor, this time utilizing the third dimension," said Intel President and CEO Paul Otellini. "Amazing, world-shaping devices will be created from this capability as we advance Moore's Law into new realms."

Scientists have long recognized the benefits of a 3-D structure for sustaining the pace of Moore's Law as device dimensions become so small that physical laws become barriers to advancement. The key to today's breakthrough is Intel's ability to deploy its novel 3-D Tri-Gate transistor design into high-volume manufacturing, ushering in the next era of Moore's Law and opening the door to a new generation of innovations across a broad spectrum of devices.


Moore's Law is a forecast for the pace of silicon technology development that states that roughly every 2 years transistor density will double, while increasing functionality and performance and decreasing costs. It has become the basic business model for the semiconductor industry for more than 40 years.

Unprecedented Power Savings and Performance Gains

Intel's 3-D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency compared to previous state-of-the-art transistors. The capabilities give chip designers the flexibility to choose transistors targeted for low power or high performance, depending on the application.


The 22nm 3-D Tri-Gate transistors provide up to 37 percent performance increase at low voltage versus Intel's 32nm planar transistors. This incredible gain means that they are ideal for use in small handheld devices, which operate using less energy to "switch" back and forth. Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32nm chips.


"The performance gains and power savings of Intel's unique 3-D Tri-Gate transistors are like nothing we've seen before," said Mark Bohr, Intel Senior Fellow. "This milestone is going further than simply keeping up with Moore's Law. The low-voltage and low-power benefits far exceed what we typically see from one process generation to the next. It will give product designers the flexibility to make current devices smarter and wholly new ones possible. We believe this breakthrough will extend Intel's lead even further over the rest of the semiconductor industry."


Continuing the Pace of Innovation – Moore's Law

Transistors continue to get smaller, cheaper and more energy efficient in accordance with Moore's Law – named for Intel co-founder Gordon Moore. Because of this, Intel has been able to innovate and integrate, adding more features and computing cores to each chip, increasing performance, and decreasing manufacturing cost per transistor.

Sustaining the progress of Moore's Law becomes even more complex with the 22nm generation. Anticipating this, Intel research scientists in 2002 invented what they called a Tri-Gate transistor, named for the three sides of the gate. Today's announcement follows further years of development in Intel's highly coordinated research-development-manufacturing pipeline, and marks the implementation of this work for high-volume manufacturing.


The 3-D Tri-Gate transistors are a reinvention of the transistor. The traditional "flat" two-dimensional planar gate is replaced with an incredibly thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin – two on each side and one across the top -- rather than just one on top, as is the case with the 2-D planar transistor. The additional control enables as much transistor current flowing as possible when the transistor is in the "on" state (for performance), and as close to zero as possible when it is in the "off" state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance).


Just as skyscrapers let urban planners optimize available space by building upward, Intel's 3-D Tri-Gate transistor structure provides a way to manage density. Since these fins are vertical in nature, transistors can be packed closer together, a critical component to the technological and economic benefits of Moore's Law. For future generations, designers also have the ability to continue growing the height of the fins to get even more performance and energy-efficiency gains.


"For years we have seen limits to how small transistors can get," said Moore. "This change in the basic structure is a truly revolutionary approach, and one that should allow Moore's Law, and the historic pace of innovation, to continue."


World's First Demonstration of 22nm 3-D Tri-Gate Transistors

The 3-D Tri-Gate transistor will be implemented in the company's upcoming manufacturing process, called the 22nm node, in reference to the size of individual transistor features. More than 6 million 22nm Tri-Gate transistors could fit in the period at the end of this sentence.


Today, Intel demonstrated the world's first 22nm microprocessor, codenamed "Ivy Bridge," working in a laptop, server and desktop computer. Ivy Bridge-based Intel® Core™ family processors will be the first high-volume chips to use 3-D Tri-Gate transistors. Ivy Bridge is slated for high-volume production readiness by the end of this year.

This silicon technology breakthrough will also aid in the delivery of more highly integrated Intel® Atom™ processor-based products that scale the performance, functionality and software compatibility of Intel® architecture while meeting the overall power, cost and size requirements for a range of market segment needs.

Thursday, April 28, 2011

Cascade Microtech Partners with imec for 3D-TSV Probe Solutions

Technology leaders collaborate on 3D-TSV test infrastructure
BEAVERTON, OR. — Cascade Microtech, Inc. (NASDAQ: CSCD), a leading expert at enabling precision measurements of integrated circuits at the wafer level, and the nanoelectronics research center imec, today announced they have entered into a collaborative research partnership for testing and characterization of 3D IC test structures. Imec will work closely with Cascade Microtech to develop test methods and methodologies for emerging 3D Through-Silicon-Via (TSV) structures, and to lead the way in development of global standards for 3D IC development and production test.
Demand for tablet PCs and smartphones is driving processor vendors to utilize 3D-TSV techniques to stack memory on processors, achieving higher performance without the need for node shrinks. 3D-TSV stacked ICs, still an emerging technology, allow multiple chips to be stacked and integrated into a single package, reducing the form factor, reducing power consumption and increasing the bandwidth of inter-chip communication by eliminating connections through the circuit board. Chip stacking with 3D-TSV interconnects requires Known-Good Die (KGD) wafer probing with high test coverage before stacking in order to achieve practical stack yields. The high density of TSV interconnects has challenged conventional probe card architectures thus limiting electrical test access.
The complexities of test inherent in new 3D-TSV IC designs will be a key focus of the research project that will take place at imec’s research facilities in Belgium, where silicon wafers with test probe structures of 40 micron pitch and smaller will be manufactured and tested. In the process of ongoing research, imec will install the first turnkey 3D test solution comprising of a 3D-TSV probe station and a new 3D-TSV probe card from Cascade Microtech. The probe station and probe cards will be used to characterize the TSV in the chip stacks as part of ongoing efforts to optimize 3D stacked IC performance and reliability.

“The complexity of the 3D-system supply chain is reflected in the partner portfolio of imec’s 3D research program where leading IDMs, foundries, fabless companies, OSATs, equipment and material suppliers as well as EDA companies partner to develop and improve 3D technologies. A good alignment of these multi-disciplinary forces is required to make 3D system integration an industrial reality,” said Erik Jan Marinissen, imec Principal Scientist. “The collaboration with Cascade Microtech in this early phase of engineering and development will enable us to identify challenges and provide solutions for test issues that are specific for 3D integrated systems. Enabling probing solutions for high-density interfaces, minimizing the impact of pre-bond testing on stacking yield and test access to buried layers are key challenges for testing 3D systems that we will address through this collaboration.
“Ongoing research is critical for Cascade Microtech’s 3D-TSV solution path, and imec is a key collaboration partner for our development efforts, given its history of successful research collaboration, its superior research facilities, its commitment to the semiconductor industry and the expertise of its staff,” said Michael Burger, President and CEO, Cascade Microtech, Inc. “In recent years, probing and test were viewed as a major barrier to 3D-TSV development and manufacturing. We are looking forward to breaking through the barrier, paving the way for our mutual customers to quickly achieve extremely cost-effective 3D-TSV test solutions.”


About ImecImec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China and Japan. Its staff of more than 1,750 people includes over 550 industrial residents and guest researchers. In 2009, imec's revenue (P&L) was 275 million euro. Further information on Imec can be found at www.imec.be.
Note: Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shangai) Co. Ltd.).

About Cascade Microtech, Inc. Cascade Microtech, Inc. (NASDAQ: CSCD) is a worldwide leader in the precise electrical and mechanical measurement and test of integrated circuits (ICs) and other small structures. For technology businesses and scientific institutions that need to evaluate small structures, Cascade Microtech delivers access to electrical data from wafers, ICs, IC packages, circuit boards and modules, MEMS, 3D TSV, LED devices and more. Cascade Microtech’s leading-edge semiconductor production test products include unique probe cards and test sockets that reduce manufacturing costs of high-speed and high-density semiconductor chips. For more information visit www.cascademicrotech.com.
FOR MORE INFORMATION, CONTACT:
Laurie A. Winton
Cascade Microtech, Inc.
(503) 601-1934
laurie.winton@cmicro.com
Katrien Marent
imec
+32 16 281 880
katrien.marent@imec.be

IC packaging report covers 12 package types + bare die, SATS providers - Advanced Packaging

New Venture Research will release "The Worldwide IC Packaging Market, 2011 Edition" in May 2011. It offers an in-depth look at the worldwide integrated circuit (IC) packaging market.

The forecasts of individual IC device markets are provided, for units, revenue, and ASP, from 2008 through 2014.

The packages for each of these markets are then forecast, broken down into I/O ranges.

In a separate chapter, the package types are rolled up to deliver an overall worldwide forecast of IC packages, divided into 12 different package families, plus bare die solutions. The major package families include:

* Dual in-line package (DIP);

* Small outline transistor (SOT);

* Small outline (SO);

* Thin small outline package (TSOP);

* Dual flat pack no lead (DFN);

* Chip carrier (CC);

* Quad flat pack (QFP);

* Quad flat pack no lead (QFN);

* Pin grid array (PGA);

* Ball grid array (BGA);

* Fine-pitched ball grid array (FBGA);

* Wafer-level package (WLP).


Additional unit forecasts cover die-mounting using direct chip attach (DCA) methods:

* Chip on board (COB);
* Flip chip on board (FCOB);
* Chip on glass (COG);
* Flip chip on glass (FCOG);
* And tape automated bonding (TAB)/tape carrier package (TCP).
Read More 

Wednesday, April 27, 2011

Electronic Digital Convergence

The five major system technologies for electronic digital convergence
  1. System-on-board (SOB). Discrete components interconnected on system boards
  2.  System-on-chip (SOC). Partial system on a single IC with two or more
    functions.
  3.  Multichip module (MCM). Package-enabled horizontal or 2D integration of two
    or more ICs for high electrical system performance.
  4.  Stacked ICs and packages (SIP). Package-enabled 3D stacking of two or more
    thinned ICs for system miniaturization.
  5.  System-on-package (SOP). Best IC and system integration for ultraminiaturization,
    multiple to mega functions, ultrahigh performance, low cost, and high reliability.
System-on-Board (SOB) Technology with Discrete Components
The current approach to manufacturing systems involves fabricating the components separately and assembling them onto system boards, as illustrated in

The strategy to miniaturize the systems in this traditional approach has been to reduce the size of each component by reducing the input-output (I/O) pitch, wiring, and insulation dimensions in each of the layers. But this approach presents major limitations to achieving digital convergence, as explained earlier. The IC packaging that is used to provide I/O connections from the chip to the rest of the system is typically bulky and costly, limiting both the performance and the reliability of the IC it packages. Systems packaging, involving the interconnection of components on a system-level board, is similarly bulky and costly with poor electrical and mechanical performance.

System-on-Chip (SOC) with Two or More System Functions on a Single Chip
Semiconductors have been the backbone of the IT industry, typically governed by Moore’s law. Since the invention of the transistor, microelectronics technology has impacted every aspect of human life by electronic products in the automotive, consumer, computer, telecommunication, aerospace, military, and medical industries by everhigher integration of transistors as indicated in Figure,



and at an ever-lower cost per transistor. This integration and cost path has led the microelectronics industry to believethat this kind of progress can go on forever, leading to a “system-on-a-chip” for all applications to form complete end-product systems. The SOC schematic shown in Figure above, for example, seeks to integrate numerous system functions on one silicon device horizontally, namely the chip. If this chip can be designed and fabricated cost effectively with computing, communication, and consumer functions (such as processor, memory, wireless, and graphics) by integrating the required components (such as antennas, filters, switches, transmitting waveguides, and other components required to form a complete end-product system), then all that is necessary to package such a system is to provide protection, external connections, power, and cooling. If this can be realized, SOC offers the promise for the highest performance and the most compact, lightweight system that can be mass-produced. This has been and continues to be the road map of IC companies.
So the key question is whether SOC can lead to cost-effective, complete end-product systems such as tomorrow’s leading-edge cell phones with digital, wireless, and sensing capabilities or biomedical implants. Researchers around the world, while making great progress, are realizing that SOC, in the long run, presents fundamental limits for computing and integration limits for wireless communications and additional non incremental costs to both. Among SOC challenges are the long design times due to integration complexities, high wafer fabrication costs and test costs, and mixed-signal processing complexities requiring dozens of mask steps and intellectual property issues. The high costs are due to the need to integrate active but disparate devices such as bipolar, CMOS, silicon germanium (SiGe), and optoelectronic ICs—all in one chip with multiple voltage levels and dozens of mask steps to provide digital, RF, optical, and MEMS-based components.
It is becoming clear that SOC presents major technical, financial, business, and legal challenges that are forcing industry and academic researchers to consider other options for semiconductors and systems. For the first time, industry may not invest in extending Moore’s law beyond 2015. This is leading the industry to explore alternative ways to achieve systems integration wherein semiconductor integration is pursued, not only horizontally by SOC, but also vertically by SIP via 3D stacking of bare or packaged ICs and by SOP. More than 50 companies are pursuing SIP.
Hence, a new paradigm that overcomes the shortcomings of both SOC and traditional systems packaging is necessary. The SOP technology described here makes a compelling case for the synergy between the IC and the package integration by means of the SOP concept, which can also be applied to SOCs and SIPs, as well as to silicon wafer, ceramic, or organic carrier platforms or boards.

Multichip Module (MCM): Package-Enabled Integration
of Two or More Chips Interconnected Horizontally

The MCM was invented back in the 1980s at IBM, Fujitsu, NEC, and Hitachi for the sole purpose of interconnecting dozens of good bare ICs to produce a substrate wafer that looked like the original wafer, since larger chips could not be produced with any acceptable yields on the original silicon wafer. These original MCMs were horizontal or twodimensional.
They started with so-called high-temperature cofired ceramics (HTCCs)—multilayer ceramics, such as alumina, metallized and interconnected with dozens of layers of either cofired molybdenum or tungsten. These then were replaced with higher-performance ceramic MCMs called low-temperature cofired ceramics (LTCCs)—made of lower-dielectricconstant ceramics such as glass-ceramics, metallized with better electrical conductors such as copper, gold, or silver-palladium. The third generation of MCMs improved further with add-on multilayer organic dielectrics and conductors of much lower dielectric constant and sputtered or electroplated copper with better electrical conductivity.

Stacked ICs and Packages (SIP): Package-Enabled IC Integration with Two or More Chip Stacking (Moore’s Law in the Third Dimension)
Here, SIP is defined as a vertical stacking of similar or dissimilar ICs, in contrast to the horizontal nature of SOC, which overcomes some of the above SOC limitations, such as latency, if the size of the chips and their thicknesses used in stacking are small. SIP is also defined often as the entire system-in-a-package. If all the system components (for example, passive components, interconnections, connectors, and thermal structures such as heat sinks and thermal interface materials), power sources, and system board are miniaturized and integrated into a complete system as described  as SOP, then there is no difference between SIP and SOP. The intellectual property issues as well as yield losses associated with dozens of sequential mask steps and large-area IC fabrication are also minimal. Clearly, this is the semiconductor companies’ dream in the short term. But there is one major issue with this approach. The SIP, defined above as stacking of ICs, includes only the IC integration and hence addresses only about 10 to 20 percent of the system by extending Moore’s law in the third dimension. If all the ICs in the stack are limited to CMOS IC processing, the end-product system is limited by what it can achieve only with CMOS processing at or below nanoscale. The above fundamental and integration barriers of SOC, therefore, remain. There are clear major benefits, however, to SIP: simpler design and design verification, a process with minimal mask steps, minimal time-tomarket, and minimal Intellectual Property (IP) issues. Because of the above-mentioned SIP benefits, however limited, about 50 IC and packaging companies alike have geared up in a big way to produce SIP-based modules.

SIP Categories

The SIP technology can be broadly classified, as shown in Figures



into two categories:
(1) stacking of bare or packaged ICs  by traditional wire-bond, TAB, or flip-chip technologies, and
(2) stacking by through-silicon vias (TSVs), without using wire bond or flip chip.



SIP and 3D packaging are often meant to be the same and are loosely referred to as the vertical stacking of  either bare or packaged dies.  3D package integration refers to stacking of ICs by means of TSV technology. SIP by Wire Bonding Three-dimensional integration of bare dies can be done using wire bonding as shown in



In this approach, the different stacked dies are interconnected using a common interposer (or package). The individual dies are connected to this interposer by wire bonds. Wire bonding is economical for interconnect densities of up to 300 I/Os. However, it suffers from the high parasitic inductance of the wire bonds. There is a lot of inductive coupling between the densely placed wire bonds which results in poor signal integrity. SIP by Flip Chip and Wire Bonding In this 3D integration technique, as shown in Figure



the bottom die of the stack is connected to the package by flip-chip bonds. All other dies on the top of it are connected to the package using wire bonds. This eliminates the wire bonds required for the bottom die, but still suffers from the high parasitics of the wire bonds for the upper dies. SIP by Flip Chip–on–Chip The bare dies are flip-chip bonded with each other in this approach of 3D integration as shown in Figure



The dies are arranged faceto-face with the Back End of Line (BEOL) areas of the dies facing each other. The bottom die is usually bigger than the top die. The bottom die is connected to the package by wire bonds. 3D Integration by Through-Silicon-via Technology Three-dimensional integration enables the integration of highly complex systems more cost-efficiently. A high degree of miniaturization and flexibility for the adaptation to different applications can be achieved by using the 3D integration technologies. It also enables the combination of different optimized technologies with the potential of low-cost fabrication through high yield, smaller footprints, and multifunctionality. Three-dimensional technologies also reduce the wiring lengths for interchip and intrachip communication. It thus provides a possible solution to the increasingly critical “wiring crisis” caused by signal propagation delays at both the board and the chip level.

It is possible to stack multiple bare dies using die-to-die vias and TSVs as shown in Figure.

The latter run through the silicon die [Front End of Line (FEOL) and BEOL] and are used to connect stacked dies. There are various technologies for via drilling, via lining, via filling, die (or wafer) bonding, and integration of the 3D stacked dies (or wafers). TSV technology can potentially achieve much higher vertical interconnect density as compared to the other approaches for 3D integration discussed above.
The dies can be bonded in a face-to-face or in a face-to-back. In the face-to-face die stacking, two dies are stacked with their BEOL areas facing each other. In the face-to back die stacking, two dies are stacked with the BEOL areas of one die facing the active area of the other die. Face-to-face bonding enables a higher via density than face-to back bonding because the two chips are connected by die-to-die vias which have sizes and electrical characteristics similar to conventional vias that connect on chip metal routing layers. On the other hand, in face-to-back bonding, the two chips are connected by TSVs which are much bigger than the BEOL vias. However, if more than two chips are to be stacked, then TSVs are necessary even for face-to-face bonding. Three-dimensional integration was initially introduced by stacking Flash (NOR/NAND) memory and SDRAM for cell phones in one thin CSP. This was later extended to Memory/Logic integration for high performance processors. Stacking of an ASIC digital signal processors (DSPs) and RF/analog chips or MEMS are the next logical developments in 3D packaging.

Si Substrate or Carrier
The concept of the silicon chip carrier was developed in 1972  at IBM where a Si substrate was used as a chip carrier instead of insulating organic or ceramic substrates. Initially, the chips were connected to the chip carrier by perimeter connections such as wire bonding. Later, the connections were replaced by flip-chip connections. Lately, TSVs have been used in the chip and the carrier. The TSVs help to develop a high-density interconnection from the chip to the carrier and from the carrier to the board. Presently, silicon chip carrier technology involves through-silicon vias (TSVs), high-density wiring, fine pitch chip-to-carrier interconnection, and integrated actives and passives. The TSVs can also be used to stack the Si chip carriers on top of one another.

SIP by Package Stacking 
Three-dimensional integration is also possible by a vertical stacking of individually tested IC packages. There are two topologies: package-inpackage (PiP) and package-on-package (PoP). PiP, as shown in Figure,



connects the stacked packages by wire bonds on a common substrate. In PoP, as shown in figure below, the stacked packages are connected by flip-chip bumps.

System-on-Package Technology (Module with the Best of IC and System Integration)
If, in fact, the system components such as batteries, packages, boards, thermal structures, and interconnections are miniaturized as described above with nanoscale materials and structures, this should lead to the second law of electronics. The SOP described in this book is exactly that, and it  achieves true system integration, not just with the best IC integration as in the past but also with the best system integration. As such, it addresses then the 80 to 90 percent of the system problems that had not been addressed, as described earlier. In contrast to IC integration by Moore’s law, measured in transistors per cubic centimeter, the SOP-based second law addresses the system integration challenges as measured in functions or components per cubic centimeter. As can be seen, the slope of the first law of electronics is very steep, driven by the unparalleled growth in the IC integration from one transistor in the 1950s to as many as a billion by 2010. The growth in the system integration, however, is very shallow as measured in components per square centimeter (cm2) on system-level boards to less than 100/cm2 in today’s manufacturing.