Electronic Digital Convergence

The five major system technologies for electronic digital convergence

1. System-on-board (SOB). Discrete components interconnected on system boards
2.  System-on-chip (SOC). Partial system on a single IC with two or more
   functions.
3.  Multichip module (MCM). Package-enabled horizontal or 2D integration of two
   or more ICs for high electrical system performance.
4.  Stacked ICs and packages (SIP). Package-enabled 3D stacking of two or more
   thinned ICs for system miniaturization.
5.  System-on-package (SOP). Best IC and system integration for ultraminiaturization,
   multiple to mega functions, ultrahigh performance, low cost, and high reliability.

System-on-Board (SOB) Technology with Discrete Components
The current approach to manufacturing systems involves fabricating the components separately and assembling them onto system boards, as illustrated in

The strategy to miniaturize the systems in this traditional approach has been to reduce the size of each component by reducing the input-output (I/O) pitch, wiring, and insulation dimensions in each of the layers. But this approach presents major limitations to achieving digital convergence, as explained earlier. The IC packaging that is used to provide I/O connections from the chip to the rest of the system is typically bulky and costly, limiting both the performance and the reliability of the IC it packages. Systems packaging, involving the interconnection of components on a system-level board, is similarly bulky and costly with poor electrical and mechanical performance.

System-on-Chip (SOC) with Two or More System Functions on a Single Chip
Semiconductors have been the backbone of the IT industry, typically governed by Moore’s law. Since the invention of the transistor, microelectronics technology has impacted every aspect of human life by electronic products in the automotive, consumer, computer, telecommunication, aerospace, military, and medical industries by everhigher integration of transistors as indicated in Figure,



and at an ever-lower cost per transistor. This integration and cost path has led the microelectronics industry to believethat this kind of progress can go on forever, leading to a “system-on-a-chip” for all applications to form complete end-product systems. The SOC schematic shown in Figure above, for example, seeks to integrate numerous system functions on one silicon device horizontally, namely the chip. If this chip can be designed and fabricated cost effectively with computing, communication, and consumer functions (such as processor, memory, wireless, and graphics) by integrating the required components (such as antennas, filters, switches, transmitting waveguides, and other components required to form a complete end-product system), then all that is necessary to package such a system is to provide protection, external connections, power, and cooling. If this can be realized, SOC offers the promise for the highest performance and the most compact, lightweight system that can be mass-produced. This has been and continues to be the road map of IC companies.
So the key question is whether SOC can lead to cost-effective, complete end-product systems such as tomorrow’s leading-edge cell phones with digital, wireless, and sensing capabilities or biomedical implants. Researchers around the world, while making great progress, are realizing that SOC, in the long run, presents fundamental limits for computing and integration limits for wireless communications and additional non incremental costs to both. Among SOC challenges are the long design times due to integration complexities, high wafer fabrication costs and test costs, and mixed-signal processing complexities requiring dozens of mask steps and intellectual property issues. The high costs are due to the need to integrate active but disparate devices such as bipolar, CMOS, silicon germanium (SiGe), and optoelectronic ICs—all in one chip with multiple voltage levels and dozens of mask steps to provide digital, RF, optical, and MEMS-based components.
It is becoming clear that SOC presents major technical, financial, business, and legal challenges that are forcing industry and academic researchers to consider other options for semiconductors and systems. For the first time, industry may not invest in extending Moore’s law beyond 2015. This is leading the industry to explore alternative ways to achieve systems integration wherein semiconductor integration is pursued, not only horizontally by SOC, but also vertically by SIP via 3D stacking of bare or packaged ICs and by SOP. More than 50 companies are pursuing SIP.

Hence, a new paradigm that overcomes the shortcomings of both SOC and traditional systems packaging is necessary. The SOP technology described here makes a compelling case for the synergy between the IC and the package integration by means of the SOP concept, which can also be applied to SOCs and SIPs, as well as to silicon wafer, ceramic, or organic carrier platforms or boards.

Multichip Module (MCM): Package-Enabled Integration
of Two or More Chips Interconnected Horizontally
The MCM was invented back in the 1980s at IBM, Fujitsu, NEC, and Hitachi for the sole purpose of interconnecting dozens of good bare ICs to produce a substrate wafer that looked like the original wafer, since larger chips could not be produced with any acceptable yields on the original silicon wafer. These original MCMs were horizontal or twodimensional.
They started with so-called high-temperature cofired ceramics (HTCCs)—multilayer ceramics, such as alumina, metallized and interconnected with dozens of layers of either cofired molybdenum or tungsten. These then were replaced with higher-performance ceramic MCMs called low-temperature cofired ceramics (LTCCs)—made of lower-dielectricconstant ceramics such as glass-ceramics, metallized with better electrical conductors such as copper, gold, or silver-palladium. The third generation of MCMs improved further with add-on multilayer organic dielectrics and conductors of much lower dielectric constant and sputtered or electroplated copper with better electrical conductivity.

Stacked ICs and Packages (SIP): Package-Enabled IC Integration with Two or More Chip Stacking (Moore’s Law in the Third Dimension)
Here, SIP is defined as a vertical stacking of similar or dissimilar ICs, in contrast to the horizontal nature of SOC, which overcomes some of the above SOC limitations, such as latency, if the size of the chips and their thicknesses used in stacking are small. SIP is also defined often as the entire system-in-a-package. If all the system components (for example, passive components, interconnections, connectors, and thermal structures such as heat sinks and thermal interface materials), power sources, and system board are miniaturized and integrated into a complete system as described  as SOP, then there is no difference between SIP and SOP. The intellectual property issues as well as yield losses associated with dozens of sequential mask steps and large-area IC fabrication are also minimal. Clearly, this is the semiconductor companies’ dream in the short term. But there is one major issue with this approach. The SIP, defined above as stacking of ICs, includes only the IC integration and hence addresses only about 10 to 20 percent of the system by extending Moore’s law in the third dimension. If all the ICs in the stack are limited to CMOS IC processing, the end-product system is limited by what it can achieve only with CMOS processing at or below nanoscale. The above fundamental and integration barriers of SOC, therefore, remain. There are clear major benefits, however, to SIP: simpler design and design verification, a process with minimal mask steps, minimal time-tomarket, and minimal Intellectual Property (IP) issues. Because of the above-mentioned SIP benefits, however limited, about 50 IC and packaging companies alike have geared up in a big way to produce SIP-based modules.

SIP Categories

The SIP technology can be broadly classified, as shown in Figures



into two categories:
(1) stacking of bare or packaged ICs  by traditional wire-bond, TAB, or flip-chip technologies, and
(2) stacking by through-silicon vias (TSVs), without using wire bond or flip chip.



SIP and 3D packaging are often meant to be the same and are loosely referred to as the vertical stacking of  either bare or packaged dies.  3D package integration refers to stacking of ICs by means of TSV technology. SIP by Wire Bonding Three-dimensional integration of bare dies can be done using wire bonding as shown in



In this approach, the different stacked dies are interconnected using a common interposer (or package). The individual dies are connected to this interposer by wire bonds. Wire bonding is economical for interconnect densities of up to 300 I/Os. However, it suffers from the high parasitic inductance of the wire bonds. There is a lot of inductive coupling between the densely placed wire bonds which results in poor signal integrity. SIP by Flip Chip and Wire Bonding In this 3D integration technique, as shown in Figure



the bottom die of the stack is connected to the package by flip-chip bonds. All other dies on the top of it are connected to the package using wire bonds. This eliminates the wire bonds required for the bottom die, but still suffers from the high parasitics of the wire bonds for the upper dies. SIP by Flip Chip–on–Chip The bare dies are flip-chip bonded with each other in this approach of 3D integration as shown in Figure

The dies are arranged faceto-face with the Back End of Line (BEOL) areas of the dies facing each other. The bottom die is usually bigger than the top die. The bottom die is connected to the package by wire bonds. 3D Integration by Through-Silicon-via Technology Three-dimensional integration enables the integration of highly complex systems more cost-efficiently. A high degree of miniaturization and flexibility for the adaptation to different applications can be achieved by using the 3D integration technologies. It also enables the combination of different optimized technologies with the potential of low-cost fabrication through high yield, smaller footprints, and multifunctionality. Three-dimensional technologies also reduce the wiring lengths for interchip and intrachip communication. It thus provides a possible solution to the increasingly critical “wiring crisis” caused by signal propagation delays at both the board and the chip level.

It is possible to stack multiple bare dies using die-to-die vias and TSVs as shown in Figure.

The latter run through the silicon die [Front End of Line (FEOL) and BEOL] and are used to connect stacked dies. There are various technologies for via drilling, via lining, via filling, die (or wafer) bonding, and integration of the 3D stacked dies (or wafers). TSV technology can potentially achieve much higher vertical interconnect density as compared to the other approaches for 3D integration discussed above.
The dies can be bonded in a face-to-face or in a face-to-back. In the face-to-face die stacking, two dies are stacked with their BEOL areas facing each other. In the face-to back die stacking, two dies are stacked with the BEOL areas of one die facing the active area of the other die. Face-to-face bonding enables a higher via density than face-to back bonding because the two chips are connected by die-to-die vias which have sizes and electrical characteristics similar to conventional vias that connect on chip metal routing layers. On the other hand, in face-to-back bonding, the two chips are connected by TSVs which are much bigger than the BEOL vias. However, if more than two chips are to be stacked, then TSVs are necessary even for face-to-face bonding. Three-dimensional integration was initially introduced by stacking Flash (NOR/NAND) memory and SDRAM for cell phones in one thin CSP. This was later extended to Memory/Logic integration for high performance processors. Stacking of an ASIC digital signal processors (DSPs) and RF/analog chips or MEMS are the next logical developments in 3D packaging.

Si Substrate or Carrier
The concept of the silicon chip carrier was developed in 1972  at IBM where a Si substrate was used as a chip carrier instead of insulating organic or ceramic substrates. Initially, the chips were connected to the chip carrier by perimeter connections such as wire bonding. Later, the connections were replaced by flip-chip connections. Lately, TSVs have been used in the chip and the carrier. The TSVs help to develop a high-density interconnection from the chip to the carrier and from the carrier to the board. Presently, silicon chip carrier technology involves through-silicon vias (TSVs), high-density wiring, fine pitch chip-to-carrier interconnection, and integrated actives and passives. The TSVs can also be used to stack the Si chip carriers on top of one another.

SIP by Package Stacking 
Three-dimensional integration is also possible by a vertical stacking of individually tested IC packages. There are two topologies: package-inpackage (PiP) and package-on-package (PoP). PiP, as shown in Figure,



connects the stacked packages by wire bonds on a common substrate. In PoP, as shown in figure below, the stacked packages are connected by flip-chip bumps.

System-on-Package Technology (Module with the Best of IC and System Integration)
If, in fact, the system components such as batteries, packages, boards, thermal structures, and interconnections are miniaturized as described above with nanoscale materials and structures, this should lead to the second law of electronics. The SOP described in this book is exactly that, and it  achieves true system integration, not just with the best IC integration as in the past but also with the best system integration. As such, it addresses then the 80 to 90 percent of the system problems that had not been addressed, as described earlier. In contrast to IC integration by Moore’s law, measured in transistors per cubic centimeter, the SOP-based second law addresses the system integration challenges as measured in functions or components per cubic centimeter. As can be seen, the slope of the first law of electronics is very steep, driven by the unparalleled growth in the IC integration from one transistor in the 1950s to as many as a billion by 2010. The growth in the system integration, however, is very shallow as measured in components per square centimeter (cm2) on system-level boards to less than 100/cm2 in today’s manufacturing.