Keeping up the trend of integration and power consumption reduction in the era of slower scaling clearly requires a new set of solutions. Chip stacking is seen by many in the industry as the technology that will enable the necessary continuum in the trend for increased integration. It is a class of solutions that has emerged as a combination of technology scaling and packaging techniques. Various flavors of chip stacking technologies have been proposed and some of them have been in production for a number of years. Stacks of packaged die interconnected using wire-bonding, flip-chip bumps or ball grid arrays, wafer-level packaging of chip stacks, and other techniques to stack and interconnect chips have been used to create products in the past. All these techniques manage to integrate more functionality in a single package and they reduce the power consumed in communication between chips since they substitute Printed Circuit Board connection with wire-bonds or solder balls which have much better electrical characteristics. To push the boundary of integration and power consumption reduction, chip stacking has taken another step. 3D stacked integrated circuit (3D SIC) is a chip stacking technique where the vertical conductors are embedded in the substrate during the manufacturing of the wafers in the foundry. This enables a very high interconnection density between neighboring die in the stack with low-capacitance interconnects.
Wafer-level packaging (WLP) goes a step further in form factor and integration density. It uses large vias through the silicon substrate to interconnect the different die. This increases the integration density and improves the form factor of the final stack compared to BGA implementations.
3D stacked integrated circuits (3D SIC) or 3D integrated circuits (3D IC) technology is the next generation in chip stacking technology. Bare die are stacked and are interconnected using vias through the substrate with very fine pitches. It is today the only practical solution that provides the capability to interconnect different die with tens of thousands of interconnects. Even though it is currently still an expensive process, it offers advantages in integration density as it results in the smallest volume, the highest performance, the smallest final form factor for the packaged stack and has by far the highest interconnection density between the die in the stack.
The above figure shows how the aforementioned chip stacking techniques score on a number of axes. Technology integration refers to the capability of integrating die or chips built using different process technologies. Interconnection density refers to the number of vertical connections that can exist per unit of area. Integration density quantifies the capability of the technique to integrate a lot of functionality in a small volume. Performance refers to latency of vertical interconnections and form factor refers to the size of the final product per functionality embedded.
Multi-chip-modules (MCMs) which incorporate many chips in a package side by side can integrate very heterogeneous chips at a good, i.e. low, cost but score rather low on the other axes, because it is still a solution that requires a lot of area and interconnections need to traverse large distances.
Chip stacks interconnected with wire-bonds are relatively good along all axes but do not excel anywhere. They are better than MCMs in integration density and form factor as they can pack more functionality in smaller volume and faster since the resulting wire bonds have better electrical characteristics. But, wire-bonding suffers from scalability issues. Wire-bonds can only connect I/O pins on the periphery of chips and the available real-estate there is limited. Hence wire-bonding cannot offer a significant increase in interconnection density.
Chip stacks interconnected with wire-bonds are relatively good along all axes but do not excel anywhere. They are better than MCMs in integration density and form factor as they can pack more functionality in smaller volume and faster since the resulting wire bonds have better electrical characteristics. But, wire-bonding suffers from scalability issues. Wire-bonds can only connect I/O pins on the periphery of chips and the available real-estate there is limited. Hence wire-bonding cannot offer a significant increase in interconnection density.
Ball grid array (BGA) stacks interconnect the different chips in the stack using arrays of solder balls. They improve on technology integration, but they are less cost-efficient compared to wire-bonded stacks. One of their main advantages includes the better electrical characteristics of the balls compared to the wire-bonds. This is especially useful in power delivery; for instance, solder balls enable better power delivery to power-hungry blocks with much supply voltage variations.
Wafer-level packaging (WLP) goes a step further in form factor and integration density. It uses large vias through the silicon substrate to interconnect the different die. This increases the integration density and improves the form factor of the final stack compared to BGA implementations.
3D stacked integrated circuits (3D SIC) or 3D integrated circuits (3D IC) technology is the next generation in chip stacking technology. Bare die are stacked and are interconnected using vias through the substrate with very fine pitches. It is today the only practical solution that provides the capability to interconnect different die with tens of thousands of interconnects. Even though it is currently still an expensive process, it offers advantages in integration density as it results in the smallest volume, the highest performance, the smallest final form factor for the packaged stack and has by far the highest interconnection density between the die in the stack.
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