3D IC packaging necessary to maintain Moore's Law ?

A 3D IC technology was viewed as necessary to maintain integrated circuit performance on the path described by Moore’s law. One issue was the projected increase in chip-operating frequencies that would lead to different clock rise and fall times within a chip as shown in



Numerous theoretical studies examined the performance of 3D ICs as a function of the number of active tiers and the placement of memory, logic, and other functions among and within the active tiers, but early attempts to build even rudimentary 3D ICs were unsuccessful. Those 3D ICs were constructed using epitaxial overgrowth or polysilicon deposition to stack silicon layers, but the transistor characteristics or transistor densities were unsatisfactory. Attempts to create vertical connections through silicon chips were frustrated by the inability to uniformly thin the chips to less than 50 mm and to insulate deep cuts etched through the thinned chips. At the same time IC technology developments led to tighter design rules and improved transistor performance so that IC progress continued to satisfy Moore’s Law. Within the last 10 years it became clear that Moore’s law could not be met solely by transistor design and fabrication innovations. Therefore, the development of an alternate technology to design and construct microelectronic systems as 3D devices became essential.