The semiconductor industry has been one of the main enablers for the boom of the information technology revolution that we have witnessed in the beginning of the twenty-first century. Each new generation of consumer electronics devices that hits the shelves boasts more features and functionality, better connection to other devices, lower cost, and better power efficiency per function. An excellent example of this trend is the evolution of the mobile phone since its proliferation in the end of the last century. Mobile phones started out by offering the minimal functionality of voice calling, then evolved to offering short messaging services and since then the features have kept piling up. State-of-the-art mobile phones in 2010 are in reality computing platforms offering extreme power efficiency, small form factor, and low cost for the offered functionality, which includes connectivity with virtually all known standards, high definition video decoding, social networking, office productivity suites, GPS plus any application the software community generates!
Consumers have gotten used to these trends and expect a further improvement with every generation of products coming out, which puts pressure on the consumer electronics manufacturers to deliver on these expectations. This translates to a continuous pursuit for low-cost and low-power integration. More and more functionalityneeds to be integrated into fewer chips to reduce the component count and the real estate of printed circuit boards. Chips with increased functionality need to be shrunk in order to reduce their cost and power consumption.
Consumers have gotten used to these trends and expect a further improvement with every generation of products coming out, which puts pressure on the consumer electronics manufacturers to deliver on these expectations. This translates to a continuous pursuit for low-cost and low-power integration. More and more functionalityneeds to be integrated into fewer chips to reduce the component count and the real estate of printed circuit boards. Chips with increased functionality need to be shrunk in order to reduce their cost and power consumption.
The key driver of this continuous improvement has been semiconductor process technology scaling that has shrunk the physical dimensions of transistors and interconnections to miniscule sizes, transistor channels measure a few tens of nanometers across. This miniaturization has increased the functionality per unit of area in chips by about a factor two every 3 years for the past five decades; the first integrated circuits in the 1960s comprised a few transistors, state-of-the-art integrated circuits in 2010 measure more than a billion transistors on a single die. Shrinking transistor sizes has provided other benefits as well; smaller transistors have lower capacitances so they are faster and consume less power each. Note that even though power per transistor is reducing, the increased level of integration is packing more of them into smaller spaces, elaborate design solutions are required to keep the chip-level power consumption low. This has fueled the evolution of electronics for decades.
This miniaturization by physical dimension scaling is slowing down as transistor channel lengths hit the range of 20–30 nm. Process technology is running into problems such as process variability, increased leakage currents, lithography limitations. Designers are forced to embed worst-case margins in the chips in order to work around these issues, which leads to an increase in power consumption. Furthermore, manufacturing ever larger chips has a negative impact on the production yield; fewer of them turn out to be fully functional. A lot of research effort is invested worldwide to overcome these problems and enable the technology scaling to continue unabated. But it is very doubtful whether technology scaling alone can keep delivering the rate of improvement it offered in the past decades.
Another source of increased integration has been advances in chip packaging. In the early days, packages housed one chip each. Later on multiple chips were being integrated in one package in various configurations, either side to side or on top of each other, and were interconnected using small wires inside the package. State-ofthe- art packaging techniques include System-in-a-Package, which integrates multiple chips of heterogeneous functionality and process technology into a single package interconnected with wire bonds.
The benefits offered by technology scaling and packaging advances are coming to an end. The desire for further integration and power efficiency is not however. Consumers still want more functionality at lower cost and higher power efficiency, probably more than ever
The benefits offered by technology scaling and packaging advances are coming to an end. The desire for further integration and power efficiency is not however. Consumers still want more functionality at lower cost and higher power efficiency, probably more than ever
0 comments:
Post a Comment