For use in a circuit or electronic product, chips or Integrated circuits must be separated from the wafer and, in most cases, put in a protective package. They may also be mounted onto the surface of a ceramic substrate as part of a hybrid circuit, put into a large package with other chips as part of a multichip module (MCM), or be connected directly on board a printed circuit, chip-on-board, or direct chip attach (COB or DCA) . All three options share some common processes. The packaging process, in addition to protecting the chip, provides an electrical connection system allowing the chip to be integrated into an electronic system, and it provides environmental protection and heat dissipation. This series of processes is known variously as packaging, assembly, or the back-end process.
In the packaging process, the chips are called dies or dice. Over the years, semiconductor packaging has lagged wafer fabrication in process sophistication and manufacturing demands. The advent of the VLSI/ULSI era in chip density has forced a radical upgrading of chip packaging technology and production automation. Higher-density chips require more input connections (I) and more output connections (O). These are referred to as the I/O count or simply the pin count. The IRTS lists pin count, cost, chip size, thickness, and temperature considerations as the primary physical drivers of packaging technology. As solid-state circuits have found more applications, the need for special package designs has increased. Higher pin counts have led to the adoption of bump/flip chip technology. Size and speed considerations have driven the use of chip scale packages in consumer products, such as cell phones and hand-held products. The harsh environments of space, automotive use, and military applications require special packages, processing, and testing to ensure high reliability in the field. These packages, processes, and tests are referred to as hi-rel. The other chips and packages are referred to as commercial parts. No longer is packaging the stepchild of the semiconductor industry. Many feel that, eventually, packaging will be the limiting factor on the growth of chip size. For the time being, however, much effort is going into new package designs, new material development, and faster and more reliable packaging processes.
The microelectronics package of today plays a significant role enabling silicon chips to meet their performance targets. Key examples of this are:
1. It is a space transformer enabling interconnect scaling and hence electrical connectivity between the silicon and the motherboard. The figure below shows the typical dimensional transitions enabled between the silicon chip and the package to allow nano-meter sized silicon devices to connect to a motherboard in a computer.
2. It is a key link in the delivery of power to the silicon chip and for the removal of heat generated by the silicon.
3. A well designed package enables high speed signaling in the computing system by minimizing reductions in signal integrity.
4. Packaging protects fragile silicon chips from environmental damage
The microelectronics package of today plays a significant role enabling silicon chips to meet their performance targets. Key examples of this are:
1. It is a space transformer enabling interconnect scaling and hence electrical connectivity between the silicon and the motherboard. The figure below shows the typical dimensional transitions enabled between the silicon chip and the package to allow nano-meter sized silicon devices to connect to a motherboard in a computer.
2. It is a key link in the delivery of power to the silicon chip and for the removal of heat generated by the silicon.
3. A well designed package enables high speed signaling in the computing system by minimizing reductions in signal integrity.
4. Packaging protects fragile silicon chips from environmental damage
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