signal processor, microbattery, and analog-to-digital (A/D) mixed signal] are stacking in three dimensions. Just as with many other new technologies, 3D IC integration still faces many critical issues. There are still many challenges in the development of 3D IC integration, some of them being:
• Design guidelines and software are not available.
• Test methods and equipment are lacking.
• Known good dies (KGDs) are required.
• Through-silicon vias (TSVs) with redistribution layers (RDLs)
usually are required.
• Microbumps usually are required.
• Equipment accuracy is necessary for alignments.
• Fast chips must be mixed with slow chips.
• Large chips must be mixed with small chips.
• Wafer thinning and thin-wafer handling during processing
are necessary.
• Thermal issues:
• The heat flux generated by stacked multifunctional chips
in miniature packages is extremely high.
• 3D circuits increase total power generated per unit surface
area.
• Chips in the 3D stack may be overheated if proper and
adequate cooling is not provided.
• The space between the 3D stack may be too small for cooling
channels (i.e., no gap for fluid flow).
• Thin chips may create extreme conditions for on-chip hot
spots.
• 3D IC stacking inspection methodology is needed.
• 3D IC stacking expertise is lacking.
• 3D IC stacking infrastructure is lacking.
• 3D IC stacking standards are lacking.
In the past few years, some of these critical issues have been studied by a number of experts. Their results have already been disclosed in diverse journals or, more specifically, in the proceedings of many conferences, symposia, and workshops whose primary emphases have been on electrical packaging and interconnection. Consequently, there is no single source of information devoted to the state of the art of 3D IC integration with WLP technology
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