State of the art packages

Low cost, miniaturization and high performance have been the driving forces of electronic packaging innovations. In first-level IC packaging, encouraged by size and cost reduction, chip scale packaging (CSP) is becoming prevalent for both low-end and high-end applications. Figure below shows the Fujitsu wafer level CSP configuration. It applies thin-film deposition techniques to redistribute the I/O circuitry on the chip surface and at the same time makes microbump interconnections available. All the fabrication processes are carried out at wafer-level. This shortens the manufacturing cycle and provides fully tested products while still at wafer stage. Wafer level CSP has become a mainstay of IC packaging for portable products such as cellular phones.

To achieve complex functions in a single-level package, multichip modules (MCMs) have been developed, mainly for high-end products. Figure below shows some pictures of MCMs. A MCM uses bare IC chips in its architecture; several bare IC chips from diverse chip manufacturing technologies are interconnected onto a high-density wiring substrate. This hybrid assembly method is very effective for implementation of prototypes. It enables functional designs to enter the marketplace several times faster than their competitors i.e. application specific integrated circuits (ASICs). In addition, by eliminating one level of packaging, the total length of chip interconnection in a MCM is reduced, which in turn decreases the parasitic inductance and capacitance of the package and therefore minimizes the signal delay. Therefore, MCM packages are extremely beneficial in products that are short on space and require a high level of performance.

Other state-of-the-art packages being developed include System-in-Package (SiP) and System-on-Package (SoP). These are the packaging solutions to system integration. A SiP can be considered as an advanced MCM. It employs high-density interconnection substrates that resemble the substrate technology in MCMs. Chips fabricated in different technologies are integrated in the same package to realize a partial system function. A SiP may contain one or more bare IC chips plus other components that are traditionally found on the system motherboard. Theses elements include pre-packaged ICs (CSPs, BGAs, MCMs etc), passive components, filters, EMI shields, connectors, lenses, antennas and mechanical parts. Some passive devices, i.e. resistors, inductors and capacitors, may be deposited on or embedded in the packaging substrate to achieve a further increase in packing density.
SoP is considered as the key packaging structure for future electronic products. It is aimed at building up a complete system function on one compact packaging substrate. In SoP, IC chips and other components are mounted on a substrate with embedded system-level functions, such as high-speed digital wiring, high-bandwidth optical waveguides, and RF elements. The substrate may also contain active devices. The end result is a fully functional electronic system that meets the aggressive size, cost and time-to-market requirements placed on future electronic products. Figure below shows some proposed architectures of SoP systems with digital, optical and RF mixed signal functions.