Package Interconnects

 Classically, the interconnects of the package are defined as first level and second level. The first level connects the silicon die to the package. This may be a wirebound or flip-chip-type interconnect. The second level is the connection between the package and system board. ex Ball Grid array.

First-level interconnections
In first-level packaging, the chip electrically communicates with the packaging substrate through I/O connections, which are commonly performed by one of the two common technologies, wire bonding or flip chip bonding.

Wire bonding is the most mature process. It is the existing interconnection method in conventional single IC packages and has also been used for some state-of-the-art packages. In this scheme, a fine metal wire (gold or aluminium, typically 20-25 μm in diameter) is connected between each chip pad and a corresponding substrate pad. The wire is welded to the pads at each end by thermosonic or thermocompression bonding. Figure below shows photos of wire bonding interconnections. This bonding process is time-consuming, since individual connection between chip and board are made sequentially. For chips containing many I/Os, the process time for each chip can become unacceptably long. Another drawback of wire bonding interconnection is the degradation of performance at high frequencies due to parasitics. The main parasitic effect is the bond wire inductance, which increases in proportion to the interconnect length. With a gold wire of 25 μm diameter, a wire bond generally introduces about 1 nH/mm of inductance into a circuit.

Flip chip interconnection has numerous advantageous over wire bonding, particularly for high-frequency and/or high-power ICs. In flip chip bonding, the active side of the chip is face-down and is connected to bonding pads on the packaging substrate via short conductive bumps. The bonds at numerous bumping sites are achieved simultaneously, leading to considerable time-saving for chips with many I/Os. Due to the short electrical path, the electrical parasitics of a flip chip bump are much lower than for a wire bond, making flip chip bonding attractive for high-frequency applications. In addition, flip chip interconnection allows the chip bonding pads to be distributed over the entire chip surface rather than being confined to the periphery as in wire bonding. As a result, the chip area is used more efficiently and the density of I/Os can be increased. For higher density connections, the short bumps also provide a thermal path for heat dissipation via the substrate.

Second-level (package-to-board) interconnections

(a) Basic types of second-level interconnection
In second-level packaging, IC packages and other components are mounted on a circuit board. The terminals of each first-level package, i.e. pins, leads or solder balls, are electrically connected with the metal wiring tracks on the circuit board. These connections are generally performed by one of three basic technologies, all based on soldering: pin-through-hole connection, surface mounting or ball-grid-array attachment [Che00]. All of the single IC packages and MCMs are classified into one of these categories.

1) Pin-through-hole (PTH) connection
This is the oldest connection approach, for components with pin terminals e.g. IC packages using DIP (dual in-line package) or PGA (pin-grid-array) forms. The mounting technology uses precision holes, drilled through the circuit board, with pads top and bottom to which the pins may be soldered. To make connection to internal wiring layers within the board, the walls of the through-holes may be plated by copper.

2) Surface mounting
This technology was developed in the mid of 1980s for mounting packages with peripheral leads, such as QFP (quad flat package). In this technology, a chip carrier is soldered to the pads on the surface of a board without requiring any through holes. This assembly technology paved the way for BGA (ball grid array) area-array connections in the late 1990s.

3) Ball grid array (BGA) attachment
This is the fastest growing method in recent years. It accounts for the main connection method for current high performance IC components, from PBGAs to the state-of-art CSPs (chip scale packages).

(b) Chip-on-board interconnection

With the ever-growing demands on low cost and small size packaging, the distinctions between conventional packaging levels are blurring. Direct chip-on-board (COB), which has been mainly used in advanced IC packages such as MCMs, is nowadays finding widespread use in system-level packaging. Wire bonding and flip-chip bonding have both been used as interconnection methods for chip-on-board assembly. However, the trend is towards flip-chip-on-board (FCOB) due to its advantages of small footprint and enhanced electrical performance.

Low-cost FCOB generally uses organic FR-4 circuit boards. A disadvantage of this board material is the large coefficient of thermal expansion (CTE) mismatch relative to silicon-based IC chips. If the assembly is subject to high temperatures at subsequent process steps, or undergoes temperature cycling in use as the device is powered on and off, stresses are created in the interfaces of the bump joints due to the CTE mismatch. These stresses, if sufficiently large, can lead to mechanical failure of one or more of the interconnects. This effect has been cited as the most common cause of failure in solder flip chip assemblies.
To alleviate the problem of CTE mismatch in FCOB, underfill encapsulant that has a CTE close to the flip chip joint is generally filled the gap between chip and organic circuit board. The underfill is dispensed along one or more edges of the chip; it flows under the chip via capillary action. Upon curing, the hard underfill serves to compensate for the thermal expansion difference between the chip and the board and mechanically bond the chip and board together. As such, underfill significantly enhances the fatigue life (reliability) of FCOB packages.