Intel 22nm 3-D Tri-Gate Transistor Technology

The vertical fins of Intel’s revolutionary tri-gate transistors passing through the gates.

New Transistors for 22 Nanometer Chips Have an Unprecedented Combination of Power Savings and Performance Gains

NEWS HIGHLIGHTS

* Intel announces a major technical breakthrough and historic innovation in microprocessors: the world's first 3-D transistors, called Tri-Gate, in a production technology.
* The transition to 3-D Tri-Gate transistors sustains the pace of technology advancement, fueling Moore's Law for years to come.
* An unprecedented combination of performance improvement and power reduction to enable new innovations across a range of future 22nm-based devices from the smallest handhelds to powerful cloud-based servers.
* Intel demonstrates a 22nm microprocessor – codenamed "Ivy Bridge" – that will be the first high-volume chip to use 3-D Tri-Gate transistors.

An illustration of a 32nm transistor compared to a 22nm transistor. On the left side is the 32nm planar transistor in which the current (represented by the yellow dots) flows in a plane underneath the gate. On the right is the 22nm 3-D Tri-Gate transistor with current flowing on 3 sides of a vertical fin.

SANTA CLARA, Calif., May 4, 2011 – Intel Corporation today announced a significant breakthrough in the evolution of the transistor, the microscopic building block of modern electronics. For the first time since the invention of silicon transistors over 50 years ago, transistors using a three-dimensional structure will be put into high-volume manufacturing. Intel will introduce a revolutionary 3-D transistor design called Tri-Gate, first disclosed by Intel in 2002, into high-volume manufacturing at the 22-nanometer (nm) node in an Intel chip codenamed "Ivy Bridge." A nanometer is one-billionth of a meter.


The three-dimensional Tri-Gate transistors represent a fundamental departure from the two-dimensional planar transistor structure that has powered not only all computers, mobile phones and consumer electronics to-date, but also the electronic controls within cars, spacecraft, household appliances, medical devices and virtually thousands of other everyday devices for decades.


"Intel's scientists and engineers have once again reinvented the transistor, this time utilizing the third dimension," said Intel President and CEO Paul Otellini. "Amazing, world-shaping devices will be created from this capability as we advance Moore's Law into new realms."

Scientists have long recognized the benefits of a 3-D structure for sustaining the pace of Moore's Law as device dimensions become so small that physical laws become barriers to advancement. The key to today's breakthrough is Intel's ability to deploy its novel 3-D Tri-Gate transistor design into high-volume manufacturing, ushering in the next era of Moore's Law and opening the door to a new generation of innovations across a broad spectrum of devices.


Moore's Law is a forecast for the pace of silicon technology development that states that roughly every 2 years transistor density will double, while increasing functionality and performance and decreasing costs. It has become the basic business model for the semiconductor industry for more than 40 years.

Unprecedented Power Savings and Performance Gains

Intel's 3-D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing an unprecedented combination of improved performance and energy efficiency compared to previous state-of-the-art transistors. The capabilities give chip designers the flexibility to choose transistors targeted for low power or high performance, depending on the application.


The 22nm 3-D Tri-Gate transistors provide up to 37 percent performance increase at low voltage versus Intel's 32nm planar transistors. This incredible gain means that they are ideal for use in small handheld devices, which operate using less energy to "switch" back and forth. Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32nm chips.


"The performance gains and power savings of Intel's unique 3-D Tri-Gate transistors are like nothing we've seen before," said Mark Bohr, Intel Senior Fellow. "This milestone is going further than simply keeping up with Moore's Law. The low-voltage and low-power benefits far exceed what we typically see from one process generation to the next. It will give product designers the flexibility to make current devices smarter and wholly new ones possible. We believe this breakthrough will extend Intel's lead even further over the rest of the semiconductor industry."


Continuing the Pace of Innovation – Moore's Law

Transistors continue to get smaller, cheaper and more energy efficient in accordance with Moore's Law – named for Intel co-founder Gordon Moore. Because of this, Intel has been able to innovate and integrate, adding more features and computing cores to each chip, increasing performance, and decreasing manufacturing cost per transistor.

Sustaining the progress of Moore's Law becomes even more complex with the 22nm generation. Anticipating this, Intel research scientists in 2002 invented what they called a Tri-Gate transistor, named for the three sides of the gate. Today's announcement follows further years of development in Intel's highly coordinated research-development-manufacturing pipeline, and marks the implementation of this work for high-volume manufacturing.


The 3-D Tri-Gate transistors are a reinvention of the transistor. The traditional "flat" two-dimensional planar gate is replaced with an incredibly thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin – two on each side and one across the top -- rather than just one on top, as is the case with the 2-D planar transistor. The additional control enables as much transistor current flowing as possible when the transistor is in the "on" state (for performance), and as close to zero as possible when it is in the "off" state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance).


Just as skyscrapers let urban planners optimize available space by building upward, Intel's 3-D Tri-Gate transistor structure provides a way to manage density. Since these fins are vertical in nature, transistors can be packed closer together, a critical component to the technological and economic benefits of Moore's Law. For future generations, designers also have the ability to continue growing the height of the fins to get even more performance and energy-efficiency gains.


"For years we have seen limits to how small transistors can get," said Moore. "This change in the basic structure is a truly revolutionary approach, and one that should allow Moore's Law, and the historic pace of innovation, to continue."


World's First Demonstration of 22nm 3-D Tri-Gate Transistors

The 3-D Tri-Gate transistor will be implemented in the company's upcoming manufacturing process, called the 22nm node, in reference to the size of individual transistor features. More than 6 million 22nm Tri-Gate transistors could fit in the period at the end of this sentence.


Today, Intel demonstrated the world's first 22nm microprocessor, codenamed "Ivy Bridge," working in a laptop, server and desktop computer. Ivy Bridge-based Intel® Core™ family processors will be the first high-volume chips to use 3-D Tri-Gate transistors. Ivy Bridge is slated for high-volume production readiness by the end of this year.

This silicon technology breakthrough will also aid in the delivery of more highly integrated Intel® Atom™ processor-based products that scale the performance, functionality and software compatibility of Intel® architecture while meeting the overall power, cost and size requirements for a range of market segment needs.

Cascade Microtech Partners with imec for 3D-TSV Probe Solutions

Technology leaders collaborate on 3D-TSV test infrastructure

BEAVERTON, OR. — Cascade Microtech, Inc. (NASDAQ: CSCD), a leading expert at enabling precision measurements of integrated circuits at the wafer level, and the nanoelectronics research center imec, today announced they have entered into a collaborative research partnership for testing and characterization of 3D IC test structures. Imec will work closely with Cascade Microtech to develop test methods and methodologies for emerging 3D Through-Silicon-Via (TSV) structures, and to lead the way in development of global standards for 3D IC development and production test.

Demand for tablet PCs and smartphones is driving processor vendors to utilize 3D-TSV techniques to stack memory on processors, achieving higher performance without the need for node shrinks. 3D-TSV stacked ICs, still an emerging technology, allow multiple chips to be stacked and integrated into a single package, reducing the form factor, reducing power consumption and increasing the bandwidth of inter-chip communication by eliminating connections through the circuit board. Chip stacking with 3D-TSV interconnects requires Known-Good Die (KGD) wafer probing with high test coverage before stacking in order to achieve practical stack yields. The high density of TSV interconnects has challenged conventional probe card architectures thus limiting electrical test access.

The complexities of test inherent in new 3D-TSV IC designs will be a key focus of the research project that will take place at imec’s research facilities in Belgium, where silicon wafers with test probe structures of 40 micron pitch and smaller will be manufactured and tested. In the process of ongoing research, imec will install the first turnkey 3D test solution comprising of a 3D-TSV probe station and a new 3D-TSV probe card from Cascade Microtech. The probe station and probe cards will be used to characterize the TSV in the chip stacks as part of ongoing efforts to optimize 3D stacked IC performance and reliability.

“The complexity of the 3D-system supply chain is reflected in the partner portfolio of imec’s 3D research program where leading IDMs, foundries, fabless companies, OSATs, equipment and material suppliers as well as EDA companies partner to develop and improve 3D technologies. A good alignment of these multi-disciplinary forces is required to make 3D system integration an industrial reality,” said Erik Jan Marinissen, imec Principal Scientist. “The collaboration with Cascade Microtech in this early phase of engineering and development will enable us to identify challenges and provide solutions for test issues that are specific for 3D integrated systems. Enabling probing solutions for high-density interfaces, minimizing the impact of pre-bond testing on stacking yield and test access to buried layers are key challenges for testing 3D systems that we will address through this collaboration.

“Ongoing research is critical for Cascade Microtech’s 3D-TSV solution path, and imec is a key collaboration partner for our development efforts, given its history of successful research collaboration, its superior research facilities, its commitment to the semiconductor industry and the expertise of its staff,” said Michael Burger, President and CEO, Cascade Microtech, Inc. “In recent years, probing and test were viewed as a major barrier to 3D-TSV development and manufacturing. We are looking forward to breaking through the barrier, paving the way for our mutual customers to quickly achieve extremely cost-effective 3D-TSV test solutions.”


About ImecImec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China and Japan. Its staff of more than 1,750 people includes over 550 industrial residents and guest researchers. In 2009, imec's revenue (P&L) was 275 million euro. Further information on Imec can be found at www.imec.be.

Note: Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shangai) Co. Ltd.).

About Cascade Microtech, Inc. Cascade Microtech, Inc. (NASDAQ: CSCD) is a worldwide leader in the precise electrical and mechanical measurement and test of integrated circuits (ICs) and other small structures. For technology businesses and scientific institutions that need to evaluate small structures, Cascade Microtech delivers access to electrical data from wafers, ICs, IC packages, circuit boards and modules, MEMS, 3D TSV, LED devices and more. Cascade Microtech’s leading-edge semiconductor production test products include unique probe cards and test sockets that reduce manufacturing costs of high-speed and high-density semiconductor chips. For more information visit www.cascademicrotech.com.

FOR MORE INFORMATION, CONTACT:

Laurie A. Winton
Cascade Microtech, Inc.
(503) 601-1934
laurie.winton@cmicro.com
Katrien Marent
imec
+32 16 281 880
katrien.marent@imec.be

IC packaging report covers 12 package types + bare die, SATS providers - Advanced Packaging

New Venture Research will release "The Worldwide IC Packaging Market, 2011 Edition" in May 2011. It offers an in-depth look at the worldwide integrated circuit (IC) packaging market.

The forecasts of individual IC device markets are provided, for units, revenue, and ASP, from 2008 through 2014.

The packages for each of these markets are then forecast, broken down into I/O ranges.

In a separate chapter, the package types are rolled up to deliver an overall worldwide forecast of IC packages, divided into 12 different package families, plus bare die solutions. The major package families include:

* Dual in-line package (DIP);

* Small outline transistor (SOT);

* Small outline (SO);

* Thin small outline package (TSOP);

* Dual flat pack no lead (DFN);

* Chip carrier (CC);

* Quad flat pack (QFP);

* Quad flat pack no lead (QFN);

* Pin grid array (PGA);

* Ball grid array (BGA);

* Fine-pitched ball grid array (FBGA);

* Wafer-level package (WLP).


Additional unit forecasts cover die-mounting using direct chip attach (DCA) methods:

* Chip on board (COB);
* Flip chip on board (FCOB);
* Chip on glass (COG);
* Flip chip on glass (FCOG);
* And tape automated bonding (TAB)/tape carrier package (TCP).
Read More 

Electronic Digital Convergence

The five major system technologies for electronic digital convergence

1. System-on-board (SOB). Discrete components interconnected on system boards
2.  System-on-chip (SOC). Partial system on a single IC with two or more
   functions.
3.  Multichip module (MCM). Package-enabled horizontal or 2D integration of two
   or more ICs for high electrical system performance.
4.  Stacked ICs and packages (SIP). Package-enabled 3D stacking of two or more
   thinned ICs for system miniaturization.
5.  System-on-package (SOP). Best IC and system integration for ultraminiaturization,
   multiple to mega functions, ultrahigh performance, low cost, and high reliability.

System-on-Board (SOB) Technology with Discrete Components
The current approach to manufacturing systems involves fabricating the components separately and assembling them onto system boards, as illustrated in

The strategy to miniaturize the systems in this traditional approach has been to reduce the size of each component by reducing the input-output (I/O) pitch, wiring, and insulation dimensions in each of the layers. But this approach presents major limitations to achieving digital convergence, as explained earlier. The IC packaging that is used to provide I/O connections from the chip to the rest of the system is typically bulky and costly, limiting both the performance and the reliability of the IC it packages. Systems packaging, involving the interconnection of components on a system-level board, is similarly bulky and costly with poor electrical and mechanical performance.

System-on-Chip (SOC) with Two or More System Functions on a Single Chip
Semiconductors have been the backbone of the IT industry, typically governed by Moore’s law. Since the invention of the transistor, microelectronics technology has impacted every aspect of human life by electronic products in the automotive, consumer, computer, telecommunication, aerospace, military, and medical industries by everhigher integration of transistors as indicated in Figure,



and at an ever-lower cost per transistor. This integration and cost path has led the microelectronics industry to believethat this kind of progress can go on forever, leading to a “system-on-a-chip” for all applications to form complete end-product systems. The SOC schematic shown in Figure above, for example, seeks to integrate numerous system functions on one silicon device horizontally, namely the chip. If this chip can be designed and fabricated cost effectively with computing, communication, and consumer functions (such as processor, memory, wireless, and graphics) by integrating the required components (such as antennas, filters, switches, transmitting waveguides, and other components required to form a complete end-product system), then all that is necessary to package such a system is to provide protection, external connections, power, and cooling. If this can be realized, SOC offers the promise for the highest performance and the most compact, lightweight system that can be mass-produced. This has been and continues to be the road map of IC companies.
So the key question is whether SOC can lead to cost-effective, complete end-product systems such as tomorrow’s leading-edge cell phones with digital, wireless, and sensing capabilities or biomedical implants. Researchers around the world, while making great progress, are realizing that SOC, in the long run, presents fundamental limits for computing and integration limits for wireless communications and additional non incremental costs to both. Among SOC challenges are the long design times due to integration complexities, high wafer fabrication costs and test costs, and mixed-signal processing complexities requiring dozens of mask steps and intellectual property issues. The high costs are due to the need to integrate active but disparate devices such as bipolar, CMOS, silicon germanium (SiGe), and optoelectronic ICs—all in one chip with multiple voltage levels and dozens of mask steps to provide digital, RF, optical, and MEMS-based components.
It is becoming clear that SOC presents major technical, financial, business, and legal challenges that are forcing industry and academic researchers to consider other options for semiconductors and systems. For the first time, industry may not invest in extending Moore’s law beyond 2015. This is leading the industry to explore alternative ways to achieve systems integration wherein semiconductor integration is pursued, not only horizontally by SOC, but also vertically by SIP via 3D stacking of bare or packaged ICs and by SOP. More than 50 companies are pursuing SIP.

Hence, a new paradigm that overcomes the shortcomings of both SOC and traditional systems packaging is necessary. The SOP technology described here makes a compelling case for the synergy between the IC and the package integration by means of the SOP concept, which can also be applied to SOCs and SIPs, as well as to silicon wafer, ceramic, or organic carrier platforms or boards.

Multichip Module (MCM): Package-Enabled Integration
of Two or More Chips Interconnected Horizontally
The MCM was invented back in the 1980s at IBM, Fujitsu, NEC, and Hitachi for the sole purpose of interconnecting dozens of good bare ICs to produce a substrate wafer that looked like the original wafer, since larger chips could not be produced with any acceptable yields on the original silicon wafer. These original MCMs were horizontal or twodimensional.
They started with so-called high-temperature cofired ceramics (HTCCs)—multilayer ceramics, such as alumina, metallized and interconnected with dozens of layers of either cofired molybdenum or tungsten. These then were replaced with higher-performance ceramic MCMs called low-temperature cofired ceramics (LTCCs)—made of lower-dielectricconstant ceramics such as glass-ceramics, metallized with better electrical conductors such as copper, gold, or silver-palladium. The third generation of MCMs improved further with add-on multilayer organic dielectrics and conductors of much lower dielectric constant and sputtered or electroplated copper with better electrical conductivity.

Stacked ICs and Packages (SIP): Package-Enabled IC Integration with Two or More Chip Stacking (Moore’s Law in the Third Dimension)
Here, SIP is defined as a vertical stacking of similar or dissimilar ICs, in contrast to the horizontal nature of SOC, which overcomes some of the above SOC limitations, such as latency, if the size of the chips and their thicknesses used in stacking are small. SIP is also defined often as the entire system-in-a-package. If all the system components (for example, passive components, interconnections, connectors, and thermal structures such as heat sinks and thermal interface materials), power sources, and system board are miniaturized and integrated into a complete system as described  as SOP, then there is no difference between SIP and SOP. The intellectual property issues as well as yield losses associated with dozens of sequential mask steps and large-area IC fabrication are also minimal. Clearly, this is the semiconductor companies’ dream in the short term. But there is one major issue with this approach. The SIP, defined above as stacking of ICs, includes only the IC integration and hence addresses only about 10 to 20 percent of the system by extending Moore’s law in the third dimension. If all the ICs in the stack are limited to CMOS IC processing, the end-product system is limited by what it can achieve only with CMOS processing at or below nanoscale. The above fundamental and integration barriers of SOC, therefore, remain. There are clear major benefits, however, to SIP: simpler design and design verification, a process with minimal mask steps, minimal time-tomarket, and minimal Intellectual Property (IP) issues. Because of the above-mentioned SIP benefits, however limited, about 50 IC and packaging companies alike have geared up in a big way to produce SIP-based modules.

SIP Categories

The SIP technology can be broadly classified, as shown in Figures



into two categories:
(1) stacking of bare or packaged ICs  by traditional wire-bond, TAB, or flip-chip technologies, and
(2) stacking by through-silicon vias (TSVs), without using wire bond or flip chip.



SIP and 3D packaging are often meant to be the same and are loosely referred to as the vertical stacking of  either bare or packaged dies.  3D package integration refers to stacking of ICs by means of TSV technology. SIP by Wire Bonding Three-dimensional integration of bare dies can be done using wire bonding as shown in



In this approach, the different stacked dies are interconnected using a common interposer (or package). The individual dies are connected to this interposer by wire bonds. Wire bonding is economical for interconnect densities of up to 300 I/Os. However, it suffers from the high parasitic inductance of the wire bonds. There is a lot of inductive coupling between the densely placed wire bonds which results in poor signal integrity. SIP by Flip Chip and Wire Bonding In this 3D integration technique, as shown in Figure



the bottom die of the stack is connected to the package by flip-chip bonds. All other dies on the top of it are connected to the package using wire bonds. This eliminates the wire bonds required for the bottom die, but still suffers from the high parasitics of the wire bonds for the upper dies. SIP by Flip Chip–on–Chip The bare dies are flip-chip bonded with each other in this approach of 3D integration as shown in Figure

The dies are arranged faceto-face with the Back End of Line (BEOL) areas of the dies facing each other. The bottom die is usually bigger than the top die. The bottom die is connected to the package by wire bonds. 3D Integration by Through-Silicon-via Technology Three-dimensional integration enables the integration of highly complex systems more cost-efficiently. A high degree of miniaturization and flexibility for the adaptation to different applications can be achieved by using the 3D integration technologies. It also enables the combination of different optimized technologies with the potential of low-cost fabrication through high yield, smaller footprints, and multifunctionality. Three-dimensional technologies also reduce the wiring lengths for interchip and intrachip communication. It thus provides a possible solution to the increasingly critical “wiring crisis” caused by signal propagation delays at both the board and the chip level.

It is possible to stack multiple bare dies using die-to-die vias and TSVs as shown in Figure.

The latter run through the silicon die [Front End of Line (FEOL) and BEOL] and are used to connect stacked dies. There are various technologies for via drilling, via lining, via filling, die (or wafer) bonding, and integration of the 3D stacked dies (or wafers). TSV technology can potentially achieve much higher vertical interconnect density as compared to the other approaches for 3D integration discussed above.
The dies can be bonded in a face-to-face or in a face-to-back. In the face-to-face die stacking, two dies are stacked with their BEOL areas facing each other. In the face-to back die stacking, two dies are stacked with the BEOL areas of one die facing the active area of the other die. Face-to-face bonding enables a higher via density than face-to back bonding because the two chips are connected by die-to-die vias which have sizes and electrical characteristics similar to conventional vias that connect on chip metal routing layers. On the other hand, in face-to-back bonding, the two chips are connected by TSVs which are much bigger than the BEOL vias. However, if more than two chips are to be stacked, then TSVs are necessary even for face-to-face bonding. Three-dimensional integration was initially introduced by stacking Flash (NOR/NAND) memory and SDRAM for cell phones in one thin CSP. This was later extended to Memory/Logic integration for high performance processors. Stacking of an ASIC digital signal processors (DSPs) and RF/analog chips or MEMS are the next logical developments in 3D packaging.

Si Substrate or Carrier
The concept of the silicon chip carrier was developed in 1972  at IBM where a Si substrate was used as a chip carrier instead of insulating organic or ceramic substrates. Initially, the chips were connected to the chip carrier by perimeter connections such as wire bonding. Later, the connections were replaced by flip-chip connections. Lately, TSVs have been used in the chip and the carrier. The TSVs help to develop a high-density interconnection from the chip to the carrier and from the carrier to the board. Presently, silicon chip carrier technology involves through-silicon vias (TSVs), high-density wiring, fine pitch chip-to-carrier interconnection, and integrated actives and passives. The TSVs can also be used to stack the Si chip carriers on top of one another.

SIP by Package Stacking 
Three-dimensional integration is also possible by a vertical stacking of individually tested IC packages. There are two topologies: package-inpackage (PiP) and package-on-package (PoP). PiP, as shown in Figure,



connects the stacked packages by wire bonds on a common substrate. In PoP, as shown in figure below, the stacked packages are connected by flip-chip bumps.

System-on-Package Technology (Module with the Best of IC and System Integration)
If, in fact, the system components such as batteries, packages, boards, thermal structures, and interconnections are miniaturized as described above with nanoscale materials and structures, this should lead to the second law of electronics. The SOP described in this book is exactly that, and it  achieves true system integration, not just with the best IC integration as in the past but also with the best system integration. As such, it addresses then the 80 to 90 percent of the system problems that had not been addressed, as described earlier. In contrast to IC integration by Moore’s law, measured in transistors per cubic centimeter, the SOP-based second law addresses the system integration challenges as measured in functions or components per cubic centimeter. As can be seen, the slope of the first law of electronics is very steep, driven by the unparalleled growth in the IC integration from one transistor in the 1950s to as many as a billion by 2010. The growth in the system integration, however, is very shallow as measured in components per square centimeter (cm2) on system-level boards to less than 100/cm2 in today’s manufacturing.

Beyond ball shear test: Microprobing chip/package stress at Stanford - Advanced Packaging

New work from Stanford University goes beyond simple bump shear testing to allow simulation of stresses exerted on chips during semiconductor packaging. The researchers are able to explore how the stresses affect back-end structures. Read More

Interconnect Reliability Tests

The microelectronic industry has a very short development cycle time. At this frenetic pace there is a strong temptation to take a “build and test” approach. This typically takes the form of a designed experiment with multiple design, material, and process settings. All of these test legs are then tested through conventional reliability tests. Should any of the experiment legs pass the reliability test then the new process or material is accepted. This method works well for establishing process parameters when the variable space is limited and reasonably well understood. That said, the method often fails when the converse is true. In those cases where it does succeed it is difficult to typically extrapolate toward future developments since the DOE is not based on an understanding of fundamental material properties.

BUMP PULL/SHEAR TECHNIQUES

Ball-shear testing is widely used in semiconductor assembly facilities to control ball-bonding production e.g. solder balls and wire bond balls. Shear stress is independent of the bonding area and has been recognized as a better indicator of bonding interface quality than shear force.
The integration of highly fragile low-K Inner Layer Dielectric (ILD) materials is critical to the reduction of signal propagation delays, which stem from continued geometric scaling of integrated circuits. As a result, the silicon backend (passivation layer, low-K ILD, silicon oxide layers) is prone to early failures if the applied thermomechanical stresses exceed the effective strength of the stack up. The Coefficient of Thermal Expansion (CTE) mismatch between silicon and the package substrate, along with the high stiffness of lead-free (Pbfree) interconnects, are the primary source of thermomechanical stresses. The problem is further exacerbated by reliability tests, such as the Highly Accelerated Stress Test (HAST) or temperature cycle, which are necessary to ascertain the life of these ILDs under "real life" conditions.

Commercially available bond strength testers are capable of conducting shear and tensile tests of wafer-level bumps. Bump shear tests are carried out using a 1-mil wide (25.4um) stylus. Bump pull tests are conducted using a 100um tweezer jaw with a 1Kg range pull cartridge. In both cases, the peak force to failure is reported. Results of strength measurements are also coupled with failure analysis methods such as Focused Ion Beam (FIB) for sample preparation, with subsequent Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray (EDX) analysis in order to validate resulting failure mechanisms.

The experimental procedure involves clamping the die through the use of a suitable sample stage and selection of appropriate tool settings such as test speed, stylus height for bump shear, and tweezer grip pressure for bump pull. The bump pull and shear techniques may be applied to testing either on singulated silicon die samples post FAB wafer assembly processes, or on dies that were first assembled on a package substrate and subsequently removed by heating the package. The latter process is used to understand the impact of assembly-related  parameters on silicon backend strength. 

Package Interconnects

 Classically, the interconnects of the package are defined as first level and second level. The first level connects the silicon die to the package. This may be a wirebound or flip-chip-type interconnect. The second level is the connection between the package and system board. ex Ball Grid array.

First-level interconnections
In first-level packaging, the chip electrically communicates with the packaging substrate through I/O connections, which are commonly performed by one of the two common technologies, wire bonding or flip chip bonding.

Wire bonding is the most mature process. It is the existing interconnection method in conventional single IC packages and has also been used for some state-of-the-art packages. In this scheme, a fine metal wire (gold or aluminium, typically 20-25 μm in diameter) is connected between each chip pad and a corresponding substrate pad. The wire is welded to the pads at each end by thermosonic or thermocompression bonding. Figure below shows photos of wire bonding interconnections. This bonding process is time-consuming, since individual connection between chip and board are made sequentially. For chips containing many I/Os, the process time for each chip can become unacceptably long. Another drawback of wire bonding interconnection is the degradation of performance at high frequencies due to parasitics. The main parasitic effect is the bond wire inductance, which increases in proportion to the interconnect length. With a gold wire of 25 μm diameter, a wire bond generally introduces about 1 nH/mm of inductance into a circuit.

Flip chip interconnection has numerous advantageous over wire bonding, particularly for high-frequency and/or high-power ICs. In flip chip bonding, the active side of the chip is face-down and is connected to bonding pads on the packaging substrate via short conductive bumps. The bonds at numerous bumping sites are achieved simultaneously, leading to considerable time-saving for chips with many I/Os. Due to the short electrical path, the electrical parasitics of a flip chip bump are much lower than for a wire bond, making flip chip bonding attractive for high-frequency applications. In addition, flip chip interconnection allows the chip bonding pads to be distributed over the entire chip surface rather than being confined to the periphery as in wire bonding. As a result, the chip area is used more efficiently and the density of I/Os can be increased. For higher density connections, the short bumps also provide a thermal path for heat dissipation via the substrate.

Second-level (package-to-board) interconnections

(a) Basic types of second-level interconnection
In second-level packaging, IC packages and other components are mounted on a circuit board. The terminals of each first-level package, i.e. pins, leads or solder balls, are electrically connected with the metal wiring tracks on the circuit board. These connections are generally performed by one of three basic technologies, all based on soldering: pin-through-hole connection, surface mounting or ball-grid-array attachment [Che00]. All of the single IC packages and MCMs are classified into one of these categories.

1) Pin-through-hole (PTH) connection
This is the oldest connection approach, for components with pin terminals e.g. IC packages using DIP (dual in-line package) or PGA (pin-grid-array) forms. The mounting technology uses precision holes, drilled through the circuit board, with pads top and bottom to which the pins may be soldered. To make connection to internal wiring layers within the board, the walls of the through-holes may be plated by copper.

2) Surface mounting
This technology was developed in the mid of 1980s for mounting packages with peripheral leads, such as QFP (quad flat package). In this technology, a chip carrier is soldered to the pads on the surface of a board without requiring any through holes. This assembly technology paved the way for BGA (ball grid array) area-array connections in the late 1990s.

3) Ball grid array (BGA) attachment
This is the fastest growing method in recent years. It accounts for the main connection method for current high performance IC components, from PBGAs to the state-of-art CSPs (chip scale packages).

(b) Chip-on-board interconnection

With the ever-growing demands on low cost and small size packaging, the distinctions between conventional packaging levels are blurring. Direct chip-on-board (COB), which has been mainly used in advanced IC packages such as MCMs, is nowadays finding widespread use in system-level packaging. Wire bonding and flip-chip bonding have both been used as interconnection methods for chip-on-board assembly. However, the trend is towards flip-chip-on-board (FCOB) due to its advantages of small footprint and enhanced electrical performance.

Low-cost FCOB generally uses organic FR-4 circuit boards. A disadvantage of this board material is the large coefficient of thermal expansion (CTE) mismatch relative to silicon-based IC chips. If the assembly is subject to high temperatures at subsequent process steps, or undergoes temperature cycling in use as the device is powered on and off, stresses are created in the interfaces of the bump joints due to the CTE mismatch. These stresses, if sufficiently large, can lead to mechanical failure of one or more of the interconnects. This effect has been cited as the most common cause of failure in solder flip chip assemblies.
To alleviate the problem of CTE mismatch in FCOB, underfill encapsulant that has a CTE close to the flip chip joint is generally filled the gap between chip and organic circuit board. The underfill is dispensed along one or more edges of the chip; it flows under the chip via capillary action. Upon curing, the hard underfill serves to compensate for the thermal expansion difference between the chip and the board and mechanically bond the chip and board together. As such, underfill significantly enhances the fatigue life (reliability) of FCOB packages.

State of the art packages

Low cost, miniaturization and high performance have been the driving forces of electronic packaging innovations. In first-level IC packaging, encouraged by size and cost reduction, chip scale packaging (CSP) is becoming prevalent for both low-end and high-end applications. Figure below shows the Fujitsu wafer level CSP configuration. It applies thin-film deposition techniques to redistribute the I/O circuitry on the chip surface and at the same time makes microbump interconnections available. All the fabrication processes are carried out at wafer-level. This shortens the manufacturing cycle and provides fully tested products while still at wafer stage. Wafer level CSP has become a mainstay of IC packaging for portable products such as cellular phones.

To achieve complex functions in a single-level package, multichip modules (MCMs) have been developed, mainly for high-end products. Figure below shows some pictures of MCMs. A MCM uses bare IC chips in its architecture; several bare IC chips from diverse chip manufacturing technologies are interconnected onto a high-density wiring substrate. This hybrid assembly method is very effective for implementation of prototypes. It enables functional designs to enter the marketplace several times faster than their competitors i.e. application specific integrated circuits (ASICs). In addition, by eliminating one level of packaging, the total length of chip interconnection in a MCM is reduced, which in turn decreases the parasitic inductance and capacitance of the package and therefore minimizes the signal delay. Therefore, MCM packages are extremely beneficial in products that are short on space and require a high level of performance.

Other state-of-the-art packages being developed include System-in-Package (SiP) and System-on-Package (SoP). These are the packaging solutions to system integration. A SiP can be considered as an advanced MCM. It employs high-density interconnection substrates that resemble the substrate technology in MCMs. Chips fabricated in different technologies are integrated in the same package to realize a partial system function. A SiP may contain one or more bare IC chips plus other components that are traditionally found on the system motherboard. Theses elements include pre-packaged ICs (CSPs, BGAs, MCMs etc), passive components, filters, EMI shields, connectors, lenses, antennas and mechanical parts. Some passive devices, i.e. resistors, inductors and capacitors, may be deposited on or embedded in the packaging substrate to achieve a further increase in packing density.
SoP is considered as the key packaging structure for future electronic products. It is aimed at building up a complete system function on one compact packaging substrate. In SoP, IC chips and other components are mounted on a substrate with embedded system-level functions, such as high-speed digital wiring, high-bandwidth optical waveguides, and RF elements. The substrate may also contain active devices. The end result is a fully functional electronic system that meets the aggressive size, cost and time-to-market requirements placed on future electronic products. Figure below shows some proposed architectures of SoP systems with digital, optical and RF mixed signal functions.

Phase Change Material Solution for Thermal Inteface Material

When it comes to electronic products, the more power, speed, and functionality jammed into a smaller package, the better. While these products are a dream for end-users, they can be a thermal management nightmare for design engineers. As the power increases, so does the heat. But, because of end-product size limitations, design engineers aren’t able to use larger heatsinks to address the issue of thermal management. In search for an overall efficient, yet compact, thermal solution, more emphasis is being placed on thermal interface materials (TIMs).

TIMs are usually supplied in two forms: solid pads formed with cured silicone rubber, and liquid compounds in the form of greases or pastes. Both types of materials contain a filler that increases thermal conductivity and, while pads are often preferred for their ease-of-use and long-term stability, greases or pastes offer better wetting, which improves overall thermal performance. With greases or pastes, however, there can be trade-offs for the gain in wetting performance. First, these materials can be somewhat messy in a production environment. Additionally, continual thermal cycling of greases can lead to liquid migration, leaving only the filler in place, which eliminates surface wetting and leads to possible field failures. The differing expansion rates of the materials on either side of the interface can create a “pumping” effect, which results in increased thermal impedance and inadequate thermal transfer.

Because they solve some of the problems associated with thermal greases, phase change materials have performed successfully in applications such as telecom base stations, electric trains, consumer electronics, and computers. These materials are used to replace air between the imperfect surfaces of a device and heatsink with a more thermally conductive material that will efficiently transfer heat from the device to the heatsink.

Phase change technology features a wax-based system that is solid at room temperature but becomes liquid once the excess heat of the device pushes the material past its melting point. This versatility provides the engineer with a material that is manufacturing-friendly while also delivering the performance necessary to meet thermal design requirements. Unlike thermal grease, the phase change compound will not migrate or “pump out” of the interface.

One of latest classes of phase-change TIMs is based on the proven platform of phase change technology, but possesses differences that provide a combination of performance and ease-of-use. Previous products featured a coating of phase-change compound applied to an aluminum or polyimide substrate. This generation of products, however, are coated directly onto release liners without the need for a substrate, improving performance. When placed in an interface and pushed past its melting point (45°C) by the electronic component’s heat emission, the compound becomes liquid and flows to fill all gaps and surface imperfections, removing air at the same time. Because there is no substrate to block the flow, the final interface thickness will be as thin as possible and based solely on the geometry of the parts. This thinner interface results in more efficient heat transfer and the spherical aluminum filler ensures heat transfer from the device to the heatsink with ultra-low thermal resistance.

Because the product is offered in a thickness that exceeds that needed to fill all gaps, the pad will generally be somewhat smaller than the area to which it is applied. For example, an application on a 31-mm-square CPU lid would require, depending on the flatness of the heatsink, a square pad between 15 mm and 20 mm. An effect of the smaller dimension is that the force from the retaining screws, bolts, or clips is exerted on a smaller area, which leads to higher pressures and increased flow properties at the compound’s phase change temperature. Due to this phenomenon and the material formulation, low thermal resistance is achieved even at low mounting pressures. This results in reduced stress on the components and limits potential damage to the device. 

Molded Flip Chip Imaging

Sonix , Inc., a leading designer and manufacturer of Scanning Acoustic Microscopes, introduces its Molded Flip Chip Imaging (MFCI) enhancement. Sonix MFCI improves image quality and defect detection in molded flip chips and packages with polyimide (PI) layers.

To improve the thermal properties (conductivity and expansion) of semiconductor packages, filler particles are added to compounds used for overmolding and underfill. When using ultrasonic inspection to identify defects (eg. cracks, voids, delaminations) in molded flip chips, these filler particles increase scattering of the ultrasonic signal, causing shadows in the images, and in some cases completely obscure solder bumps and Cu pillars, resulting in reduced image quality and inaccurate defect detection. Also, the polyimide materials (PI) used to improve the thermal properties of thinner dielectric layers attenuate the ultrasonic signal, further degrading image quality and defect detection.  Lower frequency (<100 MHz) transducers can be used to penetrate the mold compound, however, these are not ideal for inspecting solder bump and underfill defects, or for increasingly thinner die.

Sonix MFCI has been designed to reduce the impact of the scattering and attenuation effects of filler particles in mold compounds and PI layers.  Configured through Sonix WinIC, Sonix MFCI improves the spatial resolution, contrast and edge definition when inspecting samples containing materials that scatter or attenuate ultrasonic signals.

Sonix MFCI is available as an option on all Echo, Echo Pro and AutoWafer tools, and as a field upgrade on all Sonix Fusion and Vision tools.

Sonix, Inc. is a designer, developer, and manufacturer of scanning acoustic microscopes (SAM), for use in FA/QA laboratories, R&D and as part of the production process.  All Sonix systems have the CE Mark and are Semi S2/S8 compliant.

For more information on the Sonix MFCI, or Sonix's complete product line, contact Sonix, Inc., 8700 Morrissette Drive, Springfield, VA 22152; call 703-440-0222, fax: 703-440-9512 or e-mail: info@sonix.com

Top 4 MEMS suppliers rake in 1/3 total MEMS revenues - Small Times

The MEMS industry grew 25% in 2010, and the 4 largest companies grew even faster, increasing their domination of Yole Développement's annual top 30 MEMS company ranking. These giants now account for some $2.9 billion of the sector's $8.6 billion in total sales.
MEMS may still be an industry with a multitude of diverse products, but it's also increasingly an industry dominated by a limited number of big suppliers.

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Copper pillars appear in packages from Amkor to Unisem, says Vardaman

E. Jan Vardaman, president and founder of TechSearch International, delivered a keynote address at the International Conference on Electronics Packaging (ICEP) held in Nara, Japan April 13-15. One of the key messages in her presentation was the trend toward the adoption of copper (Cu) pillar as highlighted in TechSearch International’s recent study, Flip Chip and WLP: Market Projections and New Developments.

Since Intel’s adoption of copper, many companies are moving to adopt copper pillar as the technology for their flip chip applications. Intel started with the use of copper pillar in its 65nm and 45nm flip chip product lines, and is using the technology in its 32nm products. The first products were the "Presler" and "Yonah" processors, but today Intel uses the copper pillar process in all of its flip chip products, including its Atom processor.

Cu pillar with a solder cap has also been used for GaAs and silicon in RF modules for several years. Amkor has been shipping RF Power Amplifier and RF front-end modules with Cu pillar bumps for more than four years. Drivers included size, performance, and cost.

Copper pillar is also shipping in leadframe packages from companies including Carsem and Unisem. IBM developed a copper pillar process called C2 that has been introduced for wire bond die with 50µm pitch or larger. TI has recently announced its use of Cu pillar in the bottom package of its package on package (PoP) offering.

Advantages of copper pillar, or copper post as it is sometimes called, were highlighted in TSMC’s recent technology day when TSMC presented its roadmap for the technology. Vardaman noted in her keynote that "the move to copper pillar is similar to the industry's progression from the evaporated bump to the plated bump, and a major shift is expected in the 2013-14 timeframe."

Highlighted in the ICEP presentation was STATS ChipPAC’s low-cost FC-CSP based on copper columns, bond-on-lead interconnection, and molded underfill. A 20-40% lower cost over standard flip chip packages for most designs has been reported. Several subcontract assembly operations offer molded underfill, including Amkor, ASE, and STATS ChipPAC.

The tremendous interest in copper pillar was evident at ICEP with a standing-room-only crowd listening to ASE’s presentation on its plans for Cu pillar in FC-CSPs.

IMAPS: 3D IC toolset readiness, Cu bonding, interposer failings - Advanced Packaging

The recent IMAPS Global Business Council (GBC) Meeting and Device Packaging Conference (DPC) was the source of some significant new developments in the areas of 3D IC and fan-out wafer-level packaging.

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Potential opportunities for nanotechnology in electronics manufacturing

Robert Doering, Texas Instruments, Dallas, Texas, USA

In common usage, "nanotechnology" refers to structures (i.e., devices) and materials (and processes to fabricate them) that exhibit useful properties resulting from sub-100nm features. Note, however, that a somewhat vague restriction to "qualitatively new" is also usually included. For example, 90nm (or even 30nm) gate-length MOSFETs are not considered "nanotechnology" in many circles.

This point is even better illustrated via an informal poll of materials scientists and chemists at a meeting a few years ago, which indicated substantial agreement that nylon would be called a "nanotechnology" material if it had been invented "last week" rather than in 1935! Of course, this is just one of many examples from chemical synthesis illustrating the difficulty in creating a simple definition of "nanotechnology."

The current common usage of "nanotechnology" also usually implies something revolutionary rather than evolutionary. With respect to semiconductor product manufacturing, this criterion generally encourages focus on examples that are typically a decade or more from potential implementation.

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Graphene Heat Spreaders Superior to Carbon Nanotubes and Diamond for Electronic and Photonic Devices ?

The reliability and speed of electronic and optoelectronic devices strongly depend on temperature . Materials with very high thermal conductivities are required to spread the heat generated locally in such devices . Bulk copper, which is widely used as heat spreader in computers, has a thermal conductivity of ∼400 W m−1 K−1 at room temperature, but copper thin films, used as electrical interconnects, can have lower thermal conductivity (below 250 W m−1 K−1). 

The search is thus on for materials with thermal conductivities higher than that of copper.Researchers at the University of California-Riverside Nano Device Laboratory  claim that that the thermal conductivity of graphene is greater than that of diamond and carbon nanotubes, and thus is an excellent material for thermal management. Use of graphene as a thermal management component makes heat removal more efficient, and thus the devices and circuits can use more power and with extended life.Pure-carbon materials such as diamond, graphite, and carbon nanotubes have very high thermal conductivities, because the strong covalent bonding between carbon atoms results in a large phonon (lattice vibration) contribution to the thermal conductivity. Recently, graphene has attracted much attention due to its unique properties, such as very high intrinsic charge carrier mobility. 

Researchers at UC-Riverside  developed a device and associated method of heat removal from electronic optoelectronic and photonic devices via incorporation of extremely high thermally conducting channels or embedded layers made of single-layer graphene (SLG), bi-layer graphene (BLG), or few-layer graphene (FLG). The heat spreading graphene layers and the manufacturing method are detailed in U.S. Patent20100085713.

There is a trend in industry to reduce the size of semiconductor devices and integrated circuits. At the same time, the devices and circuits are designed to perform more functions. To satisfy the demands for reduced size and increased functionality, it becomes necessary to include a greater number of circuits in a given unit area. As a consequence of increased functionality and density in packaging, the devices and circuits use more power. This power is typically dissipated as heat generated by the devices. The increased heat generation, coupled with the need to reduce size, leads to an increase in the amount of heat generated per unit area. The increase in the amount of heat generated in a given unit area leads to a demand to increase the rate at which heat is transferred from the devices and circuits to heat sinks or to ambient environment in order to prevent them from becoming damaged due to exposure to excessive heat.

Graphene may be used for thermal management and high-flux cooling of electronic devices and circuits, such as field-effect transistors (FETs), integrated circuits (ICs), printed circuit boards (PCBs), three-dimensional (3D) ICs, and optoelectronic devices, such as light-emitting diodes (LEDs), and related electronic, optoelectronic, and photonic devices and circuits

Graphene, as discovered by the inventors, is characterized by extremely high thermal conductivity, which allows it to be used for heat removal. The embodiments use the flat geometry of graphene, which allows it to be readily incorporated into the device structure. The embodiments allow for better thermal management of the electronic and optoelectronic devices and circuits and reduced power consumption

Graphene may be used as a heat spreader material and incorporated into device and chip designs in ways that are not possible with other materials. The proposed embodiments of graphene heat spreaders include graphene layers in MOSFETs, integrated circuit packages, printed circuit boards and as a filler material in TIMs (Thermal Interface Materials).

There are no known applications of graphene as a heat spreader material in semiconductor devices and circuits, integrated circuit packaging, or PCBs. Most manufactured semiconductor devices and integrated circuits do not include thermal management components embedded in the substrates. Traditional means of heat removal (micro liquid cooling, air blowing, and external heat sinks) still remain ineffective for hot-spot removal in the region near drain-source current or new interconnect wiring. That region absorbs most of the generated heat and remains to be a part of the device or circuit most likely to be damaged from excessive heat. Embedding a layer of the material with high thermal conductivity in the substrate provides an increase in tolerable heat flux. Moreover, the heat propagates laterally within the graphene plane, which results in an increase in the area of heat dissipation, reduction of the heat flux, and more uniform heat absorption by the substrate.

Graphene has more than twice the thermal conductivity of diamond, allowing an increase in the rate of heat removal. Graphene temperature processing requirements are lower than those for diamond. Employing graphene as a heat spreader material in semiconductor devices, chip packaging, and PCBs makes an increase of tolerable power possible.

Graphene is a one-atom-thick layer of carbon arranged in a honeycomb lattice. The material's high electron mobility and high thermal conductivity could lead to chips that are not only faster but also better at dissipating heat. This schematic shows a three-dimensional stacked chip with layers of graphene acting as heat spreaders. At present, though, graphene is extremely costly to manufacture.

Nanotube Heat Sinks

High frequency power transistors would perform better with flip chip mounting, because replacing wire bonds with bumps reduces the electrical inductance, improving gain at higher frequencies. However, flip chip assembly, even with gold bumps, is inadequate to carry away the heat from a device producing 100 watts in a few square millimeters. Consequently, these high power devices are conventionally mounted face up on a grounded metal package placed directly on a heat sink, so that the entire back side can be a cooling path. Connection is through wire bonds, at some penalty in performance.


Fujitsu announced a solution to this problem, with the world's first successful application of carbon nanotubes as heat sinks for semiconductor devices. The higher thermal conductivity of the nanotubes compared to gold allows high power devices to to be mounted face down, with flip chip bumps replacing wire bonds. One advantage of a carbon  nanotube heat sink is that a thermal interface with a higher thermal conductivity is provided, especially when compared with thermal greases and metallic layers. Another advantage is that the thermal interface has a high mechanical strength. A further advantage is that a chemical bond is provided between the carbon nanotubes and the integrated circuit which promotes transfer of heat. A further advantage is that an improved contact between the integrated circuit and the thermal materials is provided. A further advantage is that a thinner and more uniform thermal interface is provided. 
Fujitsu’s test vehicle was an in-house gallium nitride high power transistor. Figure below schematically shows the transistor die mounted face up with wire bond connections, allowing backside heat dissipation to the substrate. 

Figurebelow  illustrates the steps in assembly. The package with carbon nanotube bumps is shown on the left. The die is flipped to face down, aligned with the nanotube bumps and attached to the package. 

Figure  below shows SEM photos of the nanotube bumps at three magnifications: first on the substrate metal; then an enlarged view of one portion of a bump; then a further enlargement of that portion, showing the vertical nanotubes. 

The multi-wall nanotubes are grown on the aluminum nitride substrate using hot-filament chemical vapor deposition (HF-CVD) of acetylene and argon gases at 650 ºC. An aluminum-iron catalyst is first patterned on the substrate, to define the bumps and control their growth.The nanotubes have minimum height of 15 micrometers, consistent with flip chip bump heights. Bump widths are limited to 10 micrometers, to match the chip pad widths. Nanotube density is estimated at 10¹¹ cm^-2. The completed substrate nanotubes are plated with about one micrometer of gold, and a standard GaN high power amplifier chip is attached by thermo-compression bonding. The electrical and thermal operating performance of the test device was compared with that of an identical die, wire-bonded with backside cooling. Eliminating the bond wires reduces inductance to ground more than 50%, increasing gain compared the face-up wire bonded device by more than 2 decibels at frequencies above 5 gigahertz. The resulting temperature increase is equivalent to face-up devices with backside mounting.

In 2002, Fujitsu was the first to demonstrate control of multi-wall nanotube length and diameter, using catalysts suitable for semiconductor interconnection. Fujitsu's ongoing development now will include increasing the site density of the carbon nanotubes to further improve heat transfer. Their goal is high frequency, high power flip chip amplifiers for mobile communication base stations. Fujitsu expects first product introduction of these devices in about three years.

Intel's Carbon Nanotube Heat Sink

Intel Corporation (Santa Clara, CA) earned U.S. Patent 7,704,791;for packaging of integrated circuits with carbon nanotube arrays to enhance heat dissipation through a thermal interface.According to inventors Valery M. Dubin and Thomas S. Dory a layer of metal is formed on a backside of a semiconductor wafer. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

As illustrated in FIG. 13, after the package (68) has been sealed a thermal interface (70) is added to the top of the heat spreader (62). A heat sink (72) is then placed on top of the package (68) to form a complete electronic assembly (74). The heat sink 72 is a thermally conductive member having a base portion (76) and heat sink fins (78). The heat sink( 72) has a rectangular cross-section a width (80) of 140 mm.

Chillin the chip.

Anyone old enough to associate the word "computer" with 1950s-era images of the original UNIVAC, with its 5200 tubes cooled by water drawn from a river, probably won't be shocked by the news that a computer could inflict a second-degree burn. Indeed, the fabled machine once failed spectacularly when a wayward fish obstructed the water's flow. Nevertheless, engineers, lulled by the ubiquitous hum of their workstations' fans, can be forgiven for thinking that the heat thrown off by a computer's innards is no longer a burning issue.

But it is. Chip designers, computer makers, assorted university researchers, and chip-packaging specialists are uniting to tackle one of the most urgent, but overlooked, of the litany of potential showstoppers looming for the global semiconductor industry: the soaring densities of heat on integrated circuits, particularly high-performance microprocessors. Researchers are studying exotic new kinds of heat-conducting "goop" that suck the heat out of a chip and convey it to heat sinks, which radiate it into the air. Still, it is a measure of the seriousness of the problem that engineers are also pursuing concepts that have been considered too elaborate and far too expensive for such a mass-produced consumer product as a personal computer. Possibilities on the horizon include tiny, self-contained evaporative cooling systems and even devices that capture the heat and turn it directly into electricity.

What has led researchers to such measures? Basic physics: virtually all the power that flows into a chip comes out of it as waste heat. Today's standard-issue Pentium 4 throws off 100watts, the same as the bulb in a child's Easy-Bake Oven and, as the hapless Swede learned, more than enough to cook meat. Divide by the area and you get a heat flux of around 30watts per square centimeter--a power density several times higher than that of a kitchen hot plate.

Addressing engineers at the 2001 IEEE International Solid State Circuits Conference, Patrick P. Gelsinger, the then chief technology officer at Intel Corp., Santa Clara, Calif., said that if the trend toward ever more fiery chips were to continue unchecked, and surely it will not, microprocessors a decade from now will be pouring out as much power as the surface of the sun, some 10000W/cm². "We need a fresh approach," Gelsinger concluded.

Heat Hurts Performance because transistors run faster when they're cool rather than hot. That's why power-mad "overclockers," in search of an additional 20–30 percent of switching speed, clap custom heat sinks and cryogenic refrigeration systems onto the microprocessors in their souped-up PCs. Heat, or rather repeated cycling from hot to cool, also shortens the life of the chip. One way it does this is by inducing mechanical stress that can literally tear a chip apart. "Typically, it's not the silicon but the package that fails," says Avram Bar-Cohen, an IEEE fellow and professor of mechanical engineering at the University of Maryland in College Park. But the silicon suffers, too. Hot copper and aluminum interconnects on the chip are also more susceptible to disintegration in a phenomenon called electromigration, a serious reliability issue. Supercomputer designers think nothing of adding chilled-water cooling and other refinements to their systems, but mass-market manufacturers have so far been unwilling to pay for such things. Garden-variety desktop computers today come with cooling equipment worth just US $3 to $5--basically a fan and a heat sink.

Computing has coasted on the fan and heat sink for quite some time. Indeed, for many in the electronics industry during much of the last decade, there was little urgency in the quest for new thermal management technology. That was thanks to the switch, in the 1980s, from ICs built using bipolar transistors to chips using today's technology, CMOS. CMOS set the clock back on the heat problem because,unlike transistors in bipolar technology, CMOS transistors draw power only when they switch from one state to another. "But by the late 1990s, we got to the same power dissipation levels we'd had with bipolars," says Bar-Cohen. "We had a 10-year free ride, using the technology we'd developed before. Now we need new ideas."

Perhaps the Biggest Bottleneck in air-cooling technology is getting the heat from the chip to the heat sink. Blocking the flow of heat are the interface between the chip itself and the lid of the chip package, if there is one, and the interface between the lid and the heat sink. Merely pressing the heat sink against the package lid won't do the trick, because microscopic roughness on both components makes for a joint full of air pockets, highly resistant to the flow of heat.
Historically, a common solution has been to fill one or both interfaces with solder, which is what the makers of power electronics systems still do. But this solution is not without its drawbacks. For one, you can't break a soldered connection without breaking the chip, which makes prototyping difficult. Even more troubling, a hard connection is liable to fail after a few thousand cycles of heat-induced expansion and contraction.
That's why most manufacturers resort to a thin layer of grease or "goop"--shorthand for thermal paste--as an interface that is soft enough to withstand expansion and contraction. Thermal paste consists of a bonding agent, say, mineral oil or epoxy, and a filler, such as silica or some more exotic substance. The filler does most of the job of conducting heat; the bonding agent holds it together and ensures that no microscopic air gaps remain between the chip and the lid or the lid and the heat sink. The problem is that the more filler you add to improve conductivity, the thicker the goop becomes, making it unable to fill all the gaps.

The Bane Of The Thermal Engineer is the cost of cooling. Designers of laptops and PCs are under extreme pressure to keep costs down and are unwilling to spring for much more than a heat sink and a fan. But you don't hear the supercomputer guys complaining about the heat--their customers are happy to pay for exotic technologies.
Another form of cooling, evaporative cooling (or phase change) was implemented  by Cray Inc., Seattle, in its X1 supercomputer, and today it is used in the SV2 model, as well. The system, from Parker Hannifin Corp., Cleveland, the main supplier of jet-fuel delivery systems to the aviation industry, sprays a fluorocarbon fluid, made by 3M, St. Paul, Minn., that has a boiling point of 56 °C. "As the microscopic droplets boil off, the bubbles create nucleation points" for more bubbles to form, says Greg Pautsch, a thermal-packaging engineer at Cray. Result: even faster boiling, letting the system sweat off 45 W/cm². Cray recently settled an intellectual property tiff over the technology with Isothermal Systems Research, Spokane, Wash.

A project being worked on at the Institute for Complex Engineered Systems at Carnegie Mellon University, in Pittsburgh, is a miniaturized evaporative system that Cristina Amon - director of the institite hopes can eventually be produced for 20 30 $ per machine (compared with the $5 or so it costs to air-cool today's standard-issue PCs). Her project, funded by the U.S. Defense Advanced Research Projects Agency (DARPA), uses microelectromechanical systems (MEMS) fabrication techniques to fashion a plate not much bigger than the chip itself but employing many tiny spray guns that bond directly to the chip.

Each nozzle shoots 100-micrometer droplets of a fluorine-based dielectric fluid at the chip's hot spots, metering the flow according to the temperature inferred from the switching speed of local transistors. The liquid boils, carrying off a big dollop of energy in the gas, which flows to a condenser. The condensate is then pumped back to the spray nozzles by a micropump. "We are removing 300 to 400 watts per square centimeter with our current prototype, all locally, on the chip," says Amon, an IEEE fellow. "But if you spread the heat a bit with conducting plates, you can easily double the amount." That would mean dissipating as much heat as even the high-performance chips are expected to produce in the foreseeable future. Best of all, as a cooling system, the technology is self-governing, working especially well precisely where it is needed most. That's because a dielectric fluid with the proper boiling point provides cooling at just the right temperature, and because it boils off faster in the hotter areas, reducing the temperature differential across the chip. Such differentials cause some parts of the chip to expand more than others, pulling the circuitry apart at the seams. Moreover, surface tension tends to suck liquid to the hotter, faster-drying parts.

Amon's system would, however, require some basic rethinking. For one thing, to preserve the coolant, the package must be hermetically sealed. The slightest leak would cause the remaining coolant to boil off even faster, and the chip would fail catastrophically. For another, the nozzle array would have to be designed concurrently with the chip, both to ensure that the chip's hot spots are spread out and to optimize the control of each nozzle.

The system, together with other heat-conducting concepts, was backed by DARPA in part because the military wants wearable computers that won't get fouled by mud or dust, as they would if they depended on a fan. And what's good for your PC may be good for you, too, someday: a few of the concepts DARPA is studying may even pave the way to air-conditioned uniforms for desert commandos or urban firefighters, and air-conditioned clothing for hot, cranky city dwellers.

 While chip designers, university researchers have been busy developing their models and pedigree of their approaches, my enthusiasts of overclocking have also explored new ways of dissipating the new found calories accompanying the faster performance.
Liquid cooling makes Mac Pro near silent even when overclocked

Flip Chip Redefined

STATS ChipPAC has taken its innovative Low Cost Flip Chip (LCFC) technology and enhanced it to achieve greater design flexibility and performance across a broader range of applications, I/O requirements and fab nodes. This enhanced technology has been renamed fcCuBE^TM to better describe its broader range of enhanced features and capabilities: flip chip with Cu Column, BOL and Enhanced Processes.

A Transformative Flip Chip Technology

fcCuBE^TM technology leverages innovations such as copper (Cu) column bump, patented Bond-on-Lead (BOL) interconnection and enhanced assembly processes such as mold underfill (MUF) to deliver high input/output (I/O) density, performance and superior reliability in advanced silicon nodes while retaining the low price points which make it competitive with mainstream semiconductor packaging solutions available today. This combination of enhancements allows greater design flexibility utilizing relaxed substrate design rules and a streamlined manufacturing process.

fcCuBE^TM packages are produced on substrates with matrix strip or singulated format, and use overmolding and saw singulation processes for strip base substrate similar to wirebond packages of the same form factor. The fcBGA is typically an exposed die package with CUF (capillary underfill); fcFBGA is typically an overmolded package; both fcBGA and fcFBGA use solder balls for second level (BGA) interconnection; fcFBGA-SDx represents a variation of fcFBGA comprising a “hybrid” stacked construction, i.e., flip chip die on the bottom and wirebond die on the top; while the fcLGA is an exposed die product that does not have solder balls.

STATS ChipPAC’s fcCuBE packages are available in ball counts ranging from 32 to > 1000 depending on body size and external terminal (BGA) pitch. Other features such as heat spreaders for thermal enhancement, surface mounted passive components, etc. that are offered with traditional fcFBGA and fcBGA packages are also available for fcCuBE^TM packages.

Features

• Bumped wafer thinning: 100µm Si thickness in production, 75µm qualified
• 0.40mm minimum package ball (BGA) pitch in production
• High density matrix strip for fcFBGA and wide boat format for singulated fcBGA
• Conventional 2/4 layer laminate, laminate build-up (BU) and ABF BU substrates
• In-house Cu column wafer bumping for 200 and 300mm wafers
• Mold underfill (MUF) and Capillary underfill (CUF optional) with Cu column bump
• Broad fab node compatibility: 180n, 65n-LK, 40/28n-ELK/ULK
• Applicable across broad package range: fcBGA, fcFBGA /-H (fcCSP) and fcPoP (3D)
• Wide range of package body sizes: 4 x 4mm to > 40 x 40mm
• Cost-effective manufacturing flow using conventional reflow process
  

End Applications

fcCuBE is a compelling solution for a wide cross section of end products in the mobile/handheld, computing and high-end network/telecom markets, including devices for wireless and portable products such as RFICs and power/analog ICs driven by miniaturization and low package parasitics, and for ASIC, graphics, computing and networking products driven by superior electrical and thermal performance.

STATS ChipPAC - A Pioneer in TSV Technology

As a longstanding leader in 3D packaging, STATS ChipPAC was one of the first Outsourced Semiconductor Assembly and Test (OSAT) providers to invest in TSV technology with a 51,000 sq. ft. R&D facility in Woodlands, Singapore dedicated to the development of next-generation wafer-level integration with TSV technology. STATS ChipPAC has developed and qualified key technology in areas such as TSV formation and metallization, bumped wafer thinning, thin wafer handling, 3D microbump bonding, wafer-level underfill and TSV assembly.

TSV is an important developing technology that utilises short, vertical electrical connections or “vias” that pass through a silicon wafer in order to establish an electrical connection from the active side to the backside of the die, thus providing the shortest interconnect path and creating an avenue for the ultimate in 3D integration. TSV technology offers greater space efficiencies and higher interconnect densities than wire bonding and flip chip stacking. When combined with microbump bonding and advanced flip chip technology, TSV technology enables a higher level of functional integration and performance in a smaller form factor.

STATS ChipPAC TSV Capabilities

TSV Post-Process (mid-end)

300mm wafers

Temp bonding/de-bonding

Backside via reveal

Silicon recess and backside metallization

Microbump technology for 50/40um u-bump plating



TSV Assembly/Packaging (back-end)

200mm and 300mm wafers

Chip-to-Wafer or Chip-to-Chip options

Microbump Flip Chip assembly

Bumped wafer thinning, planarization & via exposure

60/50/40um pitch bonding

Microbump bonding (solder, Cu column)

Thin wafer dicing

Wafer level underfill (ultra-small gap underfill process)

TSV package reliability & characterization

Developing Next-Generation 3D TSV packaging

TSV Silicon Interposer Technology

First & easier step for TSV application

Qualified tapered TSV process for low density Si interposer (sub-200um pitch)

High density Si Interposer with TSV in joint development

Potential to replace high-end organic (BU) substrates

Thinner profile, tighter pitch and high thermal/electrical performance

TSV Assembly / Packaging

STATS ChipPAC has full front- to back-end manufacturing capabilities for 200mm wafers and currently handles both chip-to-chip (C2C) and chip-to-wafer (C2W) assembly for TSV technology. This includes high density microbump capabilities in both solder and copper column, microbump bonding down to 40um pitch, thin wafer handling, wafer-level underfill, thin wafer dicing and microbumps for flip chip interconnection. Microbump technology is critical to delivering fine pitch, low profile solutions for high performance devices.

TSV Mid-end Fabrication
TSV STATS ChipPAC also offers a post-TSV “mid-end” fabrication process flow that occurs between the wafer fabrication and back-end assembly process. Mid-end processes support the advanced manufacturing requirements of 2.5D and 3D TSV, as well as wafer-level packaging, flip chip and embedded die technology. The mid-end process includes temporary bonding/de-bonding, back-side via reveal, silicon recess and back-side metallization and microbumping. Microbump is required to meet fine pitch, low profile applications in 3D TSV, stacking and assembly. STATS ChipPAC offers 60/40um pitch microbump bonding.

TSV Interposer and Assembly

TSV STATS ChipPAC offers TSV interposer fabrication to provide a “bridge” between today’s 2D packaging solutions and next-generation 3D technology. Often referred to as 2.5D technology, TSV interposers are an efficient and practical approach to die level integration.