STATS ChipPAC - A Pioneer in TSV Technology

As a longstanding leader in 3D packaging, STATS ChipPAC was one of the first Outsourced Semiconductor Assembly and Test (OSAT) providers to invest in TSV technology with a 51,000 sq. ft. R&D facility in Woodlands, Singapore dedicated to the development of next-generation wafer-level integration with TSV technology. STATS ChipPAC has developed and qualified key technology in areas such as TSV formation and metallization, bumped wafer thinning, thin wafer handling, 3D microbump bonding, wafer-level underfill and TSV assembly.

TSV is an important developing technology that utilises short, vertical electrical connections or “vias” that pass through a silicon wafer in order to establish an electrical connection from the active side to the backside of the die, thus providing the shortest interconnect path and creating an avenue for the ultimate in 3D integration. TSV technology offers greater space efficiencies and higher interconnect densities than wire bonding and flip chip stacking. When combined with microbump bonding and advanced flip chip technology, TSV technology enables a higher level of functional integration and performance in a smaller form factor.

STATS ChipPAC TSV Capabilities

TSV Post-Process (mid-end)

300mm wafers

Temp bonding/de-bonding

Backside via reveal

Silicon recess and backside metallization

Microbump technology for 50/40um u-bump plating



TSV Assembly/Packaging (back-end)

200mm and 300mm wafers

Chip-to-Wafer or Chip-to-Chip options

Microbump Flip Chip assembly

Bumped wafer thinning, planarization & via exposure

60/50/40um pitch bonding

Microbump bonding (solder, Cu column)

Thin wafer dicing

Wafer level underfill (ultra-small gap underfill process)

TSV package reliability & characterization

Developing Next-Generation 3D TSV packaging

TSV Silicon Interposer Technology

First & easier step for TSV application

Qualified tapered TSV process for low density Si interposer (sub-200um pitch)

High density Si Interposer with TSV in joint development

Potential to replace high-end organic (BU) substrates

Thinner profile, tighter pitch and high thermal/electrical performance

TSV Assembly / Packaging

STATS ChipPAC has full front- to back-end manufacturing capabilities for 200mm wafers and currently handles both chip-to-chip (C2C) and chip-to-wafer (C2W) assembly for TSV technology. This includes high density microbump capabilities in both solder and copper column, microbump bonding down to 40um pitch, thin wafer handling, wafer-level underfill, thin wafer dicing and microbumps for flip chip interconnection. Microbump technology is critical to delivering fine pitch, low profile solutions for high performance devices.

TSV Mid-end Fabrication
TSV STATS ChipPAC also offers a post-TSV “mid-end” fabrication process flow that occurs between the wafer fabrication and back-end assembly process. Mid-end processes support the advanced manufacturing requirements of 2.5D and 3D TSV, as well as wafer-level packaging, flip chip and embedded die technology. The mid-end process includes temporary bonding/de-bonding, back-side via reveal, silicon recess and back-side metallization and microbumping. Microbump is required to meet fine pitch, low profile applications in 3D TSV, stacking and assembly. STATS ChipPAC offers 60/40um pitch microbump bonding.

TSV Interposer and Assembly

TSV STATS ChipPAC offers TSV interposer fabrication to provide a “bridge” between today’s 2D packaging solutions and next-generation 3D technology. Often referred to as 2.5D technology, TSV interposers are an efficient and practical approach to die level integration.