CHIP STACKING TECHNOLOGY

Chip stacking to improve electronic implementation density was pioneered in the early 1980’s and developments continue in the 1990’s. The first 3-D modules, comprising multiple thin (i.e., 100$\mu$ m) IC layers, targeted the compact fabrication of analog processing channels for mosaic detector arrays. The technology was extended to include fabrication of high density neural networks for advanced focal plane array (FPA) applications. The 3-D packaging of digital memories began in late 1988 when 3-D DRAM, SRAM, and Flash memory modules of various capacities were demonstrated.

Two types of IC stacks have been built, namely short-stack and tall-stack configurations. Short-stacks consist of few (i.e., 4–6) stacked layers whereas tall-stacks may have as many as 128 layers. Many of the production steps are common for tall- and short-stacks.

The process flow for module fabrication begins with wafers comprising the die to be stacked. The first step is lead modification to relocate each die’s contact pads to one or two of its edges to align with the side-wall interconnect of the final chip-stack. This metallization step includes an additional layer gold and the additional capacitative loading is of the order of 1 pF/cm. All wafers are tested after rerouting. The wafers are then thinned on a diamond grinding machine. Whereas the starting wafer thickness is between 500 $\mu$ m and 750$\mu$ m, wafers destined for short-stacks are typically thinned to 250 $\mu$ m and those destined for tall-stacks are typically thinned to 100 $\mu$ m with a variation across a 150$\mu$ mm wafer of 3$\mu$ m. Occasionally, thinner layers have been used for special applications. The thinned wafers are then diced maintaining chip size being with an accuracy of 7.5 $\mu$ m. The thickness and dicing dimensions of the die are checked for statistical process control.

To form a chip-stack, its dice are laminated in custom fixtures using epoxies or other adhesives. The top layer of each short-stack is a cap chip which allows the conversion of the side-wall (i.e., chip edge) interconnect to an array format for wire-bonding. AlN is selected for cap chips to provide a better thermal match with the silicon chips in the stack and for its mechanical hardness. Excess epoxy is squeezed out until the final adhesive thickness is about 1 $\mu$m. The module faces are then lapped and polished. Silicon is then etched back on the faces of the chip-stack where the reroute lead ends are located. A polyimide passivation is spun on the exposed leads and is then polished just enough to expose the leads. The final step is metallization for the side-wall interconnect of the rerouted leads. Typically, gold is sputtered on top of the passivation layer to form T-connects with the reroute metallization as shown in Fig. Interconnect patterns are designed to minimize resistance and capacitance; pads are typically 50–100 $\mu$m wide, whereas typical bus metal stripes are 75 $\mu$ m or greater in width.

Tall-stacks are nearly complete at this point. Further processing may include bumping to allow flip-chip bonding to substrates and, for imaging tall-stacks, a detector array is bonded onto its front face. Short-stacks are also built in the same cube form as used for tall-stacks. This allows many short-stacks to be built in a

batch. For example, a short-stack may contain only six layers but as many as 12 short-stacks can be built in a single cube. Separation of the short-stacks is achieved by softening, at a moderate temperature, the thermoplastic polymer which holds them together; the layers within the short-stack being bonded with a thermosetting epoxy remain unaffected. The individual short-stacks are then attached to packages and wire-bonded.

The packages are evacuated and sealed using conventional processes.

The short-stack process is much more tolerant to stacking mismatches and run-outs in the -direction than the tall-stack imaging module. Indeed, die thickness accuracy has to be more stringent for tall-stacks so that detector arrays will mate to the stacks. In practice, tolerances of 25 m are held for tallstacks, with individual layer tolerances in the sub-micron range whereas the stacking tolerance for short-stacks is 50 m. Tall-stacks with 128 layers and short-stacks with four and five layers have been fabricated and short-stacks with many
more layers could be fabricated. Tall-stacks are typically 10–15 mm tall, whereas short-stacks are thin, being between 0.75 mm and 2.5 mm. Short-stacks are built in modules before segmentation; the pre-segmented stack being about 25 mm tall and containing 10–20 short-stacks. A summary of the typical specifications is given in Table .

Chip-stacks have been tested over a wide range of temperatures, with memory modules passing full military temperature screening of 60 C to 150 C and focal-plane modules operating at liquid Nitrogen temperatures. Environmental testing of chip-stacks has also shown that modules can handle forces over 15 000 G during operation.