3 Dimensional Circuit Fabrication Methods.

The main goal of 3D circuit processing is creating additional semiconducting layers of silicon, germanium, gallium arsenide, or other materials on top of an existing device layer on a semiconducting substrate. There are several possible fabrication technologies to form these layers. The most promising near term techniques are wafer bonding, silicon epitaxial growth, and recrystallization of polysilicon.

Figure shows a schematic of 3D circuits illustrating two different fabrication schemes. The choice of a particular technology will depend on the requirements of the integrated circuit system, manufacturability, and process compatibility with current technology. There are a variety of methods available for forming microchannels within a three-dimensional circuit, including plasma etching prior to wafer bonding, sacrificial silicon channels, and even chemical etching. Furthermore, there has been much recent research on etching vertical channels through wafers for electrical connections, which can be leveraged to provide the vertical fluidic connections needed in this research.

Wafer bonding differs from other fabrication technologies due to the opportunity for independent processing of the wafers prior to bonding. Fully processed wafers are directly bonded using various techniques leading to the completely overlapped stacking of the chips. Wafer bonding can be achieved by using polyimide adhesive layers, Cu-Cu thermocompression method and microbumps with liquid epoxy injection. The wafer bonding process preserves electrical characteristics of each device layer and can be repeated without damaging existing circuits. The alignment tolerance of 1–2 $\mu$m requires careful design of vertical interlayer interconnections.

Silicon epitaxial growth technique utilizes epitaxially grown single-crystal Si islands as device layers. Single-crystal Si islands are formed out of the open seed window by selective epitaxial growth, epitaxial lateral overgrowth, and chemical mechanical polishing of excess Si. The major limitation of this technique is high process temperatures (~1000°C), which results in significant degradation in the lower device layers especially with metallization layers. Although low-temperature epitaxial Si can be obtained using ultra-high-vacuum systems and utilizing plasma, this process is not yet feasible for manufacturing.

Recrystallization of polysilicon is another method for forming a second Si layer. This technique deposits polysilicon and induces recrystallization of the polysilicon film using intense laser or electron beams to enhance the performance of the thin-film transistors (TFTs). This technique requires high process temperatures during the melting of polysilicon layers. Beam-recrystallized polysilicon TFTs also exhibit low carrier mobility and unintentional impurity doping. Local crystallization, induced by patterned seeding of Ge or by metal-induced lateral crystallization, can enhance TFT performance.