Major applications for 3D TSV include CMOS image sensors, memory, processors, and other logic devices such as field programmable gate arrays (FPGAs). Each application has different requirements, therefore features and aspect ratios will vary. Different TSV fabrication processes may be used for each application. While through vias have been used in MEMS applications for many years; this market overview focuses on applications outside the MEMS area.
The first application of the technology in production today is CMOS image sensors. Production lines at Toshiba were installed in 2008, and commercial products have been shipped for mobile phone applications. Aptina (Micron’s spin-off), Oki Electric, STMicroelectronics, and Tessera with modifications to the ShellCase technology have announced image sensor products for camera modules. Today’s applications use a backside via formation process. The addition of DSP to image sensors is anticipated in future camera module versions.
Memory
Issues include concerns that high-speed memory such as DDR3 will suffer performance limitations when connected in a stacked package using wire bond technology. 3D TSV memory technology developments have been announced by Samsung Electronics, Micron Technology, NEC, Elpida, Oki Electric, Hynix, and Tezzaron. Some companies predicted that at the 32 nm node in 2010, a 3?memory density could be achieved using TSV technology. While some companies are targeted at mobile phones and other portable devices with sufficient RAM to run high-definition video and other 3D graphics applications, the first commercial application for DRAM with TSVs is expected to be high-performance memory for the server market starting in 2012.
Samsung’s developments include an all-DRAM stacked memory packaging using TSV technology. Prototypes using the company’s wafer level-processed stacked package (WSP) consist of four 512 MB DDR2 DRAMs for a combined 2 GB of high-density memory and a 4 GB DIMM stack made up of TSV-processed 2 GB DRAMs. Samsung stated that it was developing the process for next-generationcomputer systems in 2010 and beyond. Samsung has also published the results of its 3D DRAM that supports four-rank operations with a single master and three slave chips connected using approximately 300 TSVs. The total device density is 8 GB and each stack constitutes a rank. The master acts as a buffer that isolates the channel and the slave chips. Samsung reported both improved performance and lower power consumption for these prototypes .
Tezzaron has developed a process for high-volume 3D memory that is repairable, with smaller capacitances and with low manufacturing costs. The company is expected to begin selling a high-performance 3D SRAM replacement that will be less expensive to produce than the existing high-end SRAMs.
Some companies have also discussed the possibility of TSVs for flash memory applications. Examples of NAND flash memory applications include memory storage cards, USB drives, MP3 players such as Apple’s iPod, digital cameras, and portable gaming machines. Samsung has noted that the demand for smaller and smaller NAND flash card form factors is increasing at a rapid rate. Samsung representatives have indicated that future flash applications may require TSV to meet performance/form factor requirements. Other industry experts are pessimistic about shrinking design rules for NAND flash beyond the 32 nm generation because memory cells will be so small that operation will be unstable. The big problem is not the transistors, but the increase in delay.
Here is an interesting discussion on 3D packaging by the industry leaders.
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