3D System on Package.

System on Chip is a system integration approach that integrates large numbers of transistors as well as various mixed-signal active and passive components onto a single chip. However, the systems community is beginning to realize that this paradigm has fundamental engineering and investment limits. This realization led to the 3D system-in-package (SiP) approach, alternatively called 3D ICs or 3D stacked die/package. This approach lets designers stack multiple ICs or multiple-package stacked ICs at a far lower cost and in less space. The vertical die-to-die via pitch in a 3D stacked die is very small, so designers can arrange digital functional modules across multiple die at a fine level of granularity. This results in shorter wires, which translates into less wire delay and less power consumption. The SiP provides major opportunities in both miniaturization and integration for advanced and portable electronic products, but as a subsystem it is still limited by the CMOS process, just as the SoC is. Designers can take SiP a step further by embedding both active and passive components, but passive-component embedding is bulky and requires thick-film discrete components.

Thick-filmcomponent embedding distinguishes SiP from system on package (SoP), an emerging 3D system integration concept that involves embedding both active and passive components. SoP, however, incorporates ultrathin films at microscale to embed the passive components, and the package rather than the board is the system. SoP can address the shortcomings of both SoC and SiP, as well as those of traditional packaging, which is bulky, cost- ly, and lower in performance and reliability. With SoP, improvement comes in two ways: First, SoP uses CMOS based silicon for its best purpose that
is, for transistor integration; second, SoP uses the package for its best purpose—RF, optical, and digital com- ponent integration using IC-package-system codesign. SoP overcomes both the computing and integration limitations of SoC, SiP, multichip modules (MCMs), and traditional system packaging by having global wiring as well as RF, digital, and optical component integration in the package instead of on the chip. Moreover, 3D SoP addresses the wire delay problem by enabling the replacement of long, slow global interconnects with short, fast vertical routes. 

Several fundamental enabling technologies support 3D SoP integration.

• Electrical interconnect. With the availability of high density substrates with 3.5-micron line widths, SoP provides a unique opportunity for offloading global wiring to the package for enhanced performance. Key recent developments in next-generation build- up microvias for the SoP substrate include the integration of ultra-low-loss and high-k dielectrics, conductor geometries with submicron precision, and low-cost processes for multilayer stacked via interconnects.
• Chip-to-package interface. The current approach of lead-free solders with underfill presents major challenges in both dispensing the underfill and guaranteeing fatigue resistance as solder bumps shrink in height. Recent SoP research advances concerning the chip-to-package inter- face include the extension of solder bumps to stretched-solder columns and improvements in underfill technology.
• High-quality embedded passives. Designers use multilayer ceramic and multilayer organic structures with liquid crystal polymer technology to embed passives efficiently, including high-Q inductors, capacitors, matching networks, low-pass and band-pass filters, baluns, combiners, and antennas. The 3D design approach using multilayer topologies leads to high- quality, compact components to support multiple bands and standards and wider bandwidth in a compact form factor and at low cost.
• Analog/RF components. The recent development of thin-film RF materials and processes lets designers bring the SoP concept into the RF world to meet the stringent needs of wireless communication. Researchers are addressing critical issues such as board compatible embedded antennas and switches, low-loss and low-cost boards, low-crosstalk embedded transmission lines, and single mode packages, as well as design rules for vertically integrated transceivers over a wide frequency range.
• Optical interconnect. A high-speed optical clock and data transport simplify the digital architecture by requiring fewer parallel transmission lines. Moreover, optical links have low crosstalk and are not susceptible to electromagnetic interference (EMI) noise. Researchers have developed a low-temperature polymer process for fabricating and integrating opto-electronic components such as a microlens array, lasers, waveguides, splitters, couplers, gratings, and photodetectors on printed wiring boards for mixed- signal SoP applications.

Although 3D SoP manufacturing technology continues to advance, research into how to actually apply the technology lags. The complexity of designing large- scale 3D SoPs with various objectives and under multi- ple constraints has made CAD tools indispensable. In contrast to the active CAD research effort in mixed-signal SoCs and 3D stacked ICs, CAD research for 3D SoPs has a short history. Early efforts in pioneering physical design research for SoPs by no means cover existing and emerging 3D SoP physical CAD issues to their fullest extent. This article presents three physical design algorithms for fast design of reliable 3D SoPs.