Silicon interposer cost redux goal of GA Tech consortium.

Current work developing silicon interposers takes advantage of existing and depreciated 200 and 300mm wafer fabs, using back end of line (BEOL) tools and processes as well as the newly developed TSV technology for 3D ICs. Georgia Tech PRC believes such silicon interposers are limited in performance by high electrical loss of silicon and high cost of wafer-based interposers.