Microchannel Cooling for 3D Electronic Circuit

3D circuits pose thermal management challenges due to the significant increase in total power generated per unit available surface area for cooling. Furthermore, the power generated per unit volume within a 3D circuit can vary significantly, yielding large junction temperature non uniformities that can impair the collective operation of the circuit. Another problem is that the increased functionality of the circuit demands greater surface area for input and output of electrical, optical, RF, and other types of signals, which further reduces the surface area available for heat removal. While the semiconductor research community is actively studying the electrical performance and manufacturing methods of 3D circuits with as many as one hundred device layers, the introduction of a new cooling approach is a critical issue in its implementation.
The heat removal problem is particularly challenging for vertically integrated circuit technologies. The first attempts at thermal analysis of 3D ICs addressed concerns regarding heating effects in 3D complementary metal-oxide-semiconductor and investigated the effects of the silicon thickness of the upper chip layers. Previous thermal analysis was performed through device-level or chip-level modeling, showing that thermal packaging technologies with thermal resistance below 0.5 K/W will be necessary to obtain reasonable chip temperature in 3D ICs. It is also reported that metal thermal vias and Cu bonding layers in 3D integration could be helpful for heat removal in 3D ICs.