3D Network on Chip

Network-on-chip (NoC) is a general purpose on-chip interconnection network architecture that is proposed to replace the traditional design-specific global on chip wiring, by using switching fabrics or routers to connect processor cores or processing elements (PEs).

Typically, the PEs communicate with each other using a packet-switched protocol. Even though both 3D integrated circuits and NoCs are proposed as alternatives for the interconnect scaling demands, the challenges of combining both approaches to design three-dimensional NoCs have not been addressed until recently. Researchers have studied various NoC router design with 3D integration technology. For example, various design options of the NoC router for 3D NoC has been investigated:

(1) symmetric NoC router design with a simple extension to the 2D NoC router;

(2) NoC-bus hybrid router design which leverage the inherent asymmetry in the delays in a 3D architecture between the fast vertical interconnects and the horizontal interconnects that connect neighboring cores;

(3) true 3D router design with major modification as dimensionally decomposed router;

(4) multilayer 3D NoC router design which partitions a single router to multiple layers to boost the performance and reduce the power consumption. Three-dimensional NoC topology design was also investigated.

The Intel 80-core TeraFLOPS processor is a proof-of-concept of the 3D network- on-chip architecture. The 80-core chip is arranged as an 8 × 10 array of PE cores and packet-switched routers, connecting with a mesh topology. Each PE core contains two pipelined floating-point multiply accumulators (FPMAC), connecting with the router through the router interface block (RIB). The router is a five-port crossbar-based design, with mesochronous interface (MSINT). To provide a high memory bandwidth at a relative low power, 20 MB SRAM layer is stacked on top of 80-core layer, with 256 KB per core, connecting with the bus to the core. The resulting 3D NoC-bus hybrid design can provide a memory bandwidth of 12 GB/s/ core (totally 1 TB/s for the whole chip), while the mesh NoC network provides a bisection bandwidth of 2 TB/s.