Thermofluidic consideration for 3D ICs

Three-dimensionally stacked ICs bring several challenges in thermal management. By stacking layers, the heat dissipation per unit volume and per unit horizontal footprint area are significantly increased. Also, the interior layers of the 3D structure are thermally detached from the heat sink. Heat transfer is further restricted by the low thermal conductivity bonding interfaces and thermal obstacles in multiple IC layers. Moreover, the inherent spatial nonuniformity of the power/heat flux distribution/dissipation within each active layer generates local hot spots in temperature, which degrade the functionality of circuits and create thermal stress issues,due to nonuniform thermal expansion.
Conventional cooling techniques, which depend on heat sinks on the backs of ICs to transfer heat into streams of forced air, will be unable to meet the needs of future power-hungry devices – especially 3D multichip modules that will pack more processing power into less space. Several kinds of advanced cooling technologies have been presented mainly for 2D ICs, including microjet impingement cooling, compact thermosyphon, loop heat pipe, electro-osmotic pumping loop, stacked microchannel heat sink, thermoelectric microcooler, miniature vapor compression heat pump system, and miniature absorption heat pump system. However, such cooling solutions for 2D planar circuits have difficulties to overcome the limited surface area available for thermal management and the large vertical thermal resistance between the bottom layer and the heat sink of 3D integrated circuits.

Microfluidic Channel-Based Cooling

Unlike air-cooled heat sinks, liquid cooling using microchannels offers a larger heat transfer coefficient (and thus lower thermal resistance) and chip-scale cooling solution.

The above figure shows the SEM image of fabricated microfluidic channel. Recent advancement on  wafer-level fabrication technique provides polymer pipes that allow electronic and cooling interconnections to be made simultaneously using automated manufacturing processes. The low-temperature technique, which is compatible with conventional microelectronics manufacturing processing, allows fabrication of the microfluidic cooling channels without damage to integrated circuits. By controlling average operating temperature and cooling hotspots, liquid cooling can enhance reliability of the integrated circuits. Lower operating temperatures also mean a smaller thermal excursion between silicon and low-cost organic package substrates that expand at different rates.

Above figure shows an illustration of 4-tier 3D IC with microfluidic channel-based cooling. The coolant utilizes the following “thermal interconnect” path to cool individual dies in the 3D stack:
(1) packaging substrate,
(2) fluidic IO bump,
(3) fluidic TSVs,
(4) fluidic channel in each die.
The hot liquid exiting the system is cooled using an external freezer and reenters the system. Note that the fluidic TSVs are located outside the core region of the dies, thereby not causing any interference with the circuitry in each tier.