3D circuits versus 3D packages

In the popular 3D stacked-IC form of 3D integration, the mostly digital subsystem components form a stack of multiple die. In such an IC, it’s possible to fabricate transistors atop other transistors, resulting in multiple layers of active components. These transistors can then be wired to other transistors on the same device layer, to transistors on different device layers, or both, depending on the process technology. The several approaches to fabricating 3D ICs or 3D-compatible transistors vary in terms of the maximum number of device layers and the maximum density of interconnects between these layers. One leading approach is the wafer bonding method, which glues discrete wafers together using a copper interconnect interface. This low-cost method lets designers implement 3D interconnects for many wafers, overcoming the limitations of other proposed methods.

The above table compares 3D ICs and 3D SoPs in terms of their basic enabling technologies and physical design challenges. The basic processes behind the physical design of 3D ICs and 3D SoPs are similar: placement of multiple components into multiple device layers, and routing using multiple groups of multiple metal layers and various types of vias. However, component sizes in 3D ICs are in the nano- to microscale, and the total device and interconnect count is in the millions or billions. Therefore, it takes a hierarchical design methodology with design reuse to handle the complexity. On the other hand, 3D SoPs contain only hundreds to thousands of devices and interconnects, and these are in the micro- to milliscale. Therefore, a nonhierarchical design approach is sufficient for most cases. However, the SoP signal type is a mixture of digital, analog, and optical signals. Signal and power integrity challenges increase exponentially in mixed-signal systems that integrate RF front ends with optical signaling and digital baseband processing. Because designers use a highly complex and time-consuming mixed-signal noise-analysis tool to validate 3D SoP designs during the physical design process, design time and effort are at least as great as for 3D ICs.