3D Integration Technology on Microprocessor Design

The 3D integration technologies can be classified into one of the two following categories.

Industry experts on 3D stacking


(1) Monolithic approach.

This approach involves sequential device process. The frontend processing (to build the device layer) is repeated on a single wafer to build multiple active device layers before the backend processing builds interconnects among devices.

(2) Stacking approach,

which could be further categorized as wafer-to-wafer, die-to-wafer, or die-to-die stacking methods. This approach processes each layer separately, using conventional fabrication techniques. These multiple layers are then assembled to build up 3D IC, using bonding technology. Since the stacking approach does not require the change of conventional fabrication process, it is much more practical compared with the monolithic approach, and become the focus of recent 3D integration research.

Several 3D stacking technologies have been explored recently, including wire bonded, microbump, contactless (capacitive or inductive), and through-silicon vias (TSV) vertical interconnects. Among all these integration approaches, TSVbased 3D integration has the potential to offer the greatest vertical interconnect density, and therefore is the most promising one among all the vertical interconnect technologies.

Three-dimensional stacking can be carried out using two main techniques:
(1) face-to-face (F2F) bonding: two wafers (dies) are stacked so that the very top metal layers are connected. Note that the die-to-die interconnects in face-to-face wafer bonding does not go through a thick buried Silicon layer and can be fabricated as microbump. The connections to C4 I/O pads are formed as TSVs; 

(2) faceto- back (F2B) bonding: multiple device layers are stacked together with the top metal layer of one die is bond together with the substrate of the other die, and direct vertical interconnects which are called TSV tunneling through the substrate. In such F2B bonding, TSVs are used for both between-layer-connections and I/O connections.

Above figure shows a conceptual two-layer 3D IC with F2F or F2B bonding, with both TSV and microbump connections between the layers.

All TSV-based 3D stacking approaches share the following three common process steps :
(a) TSV formation;
(b) wafer thinning; and
(c) aligned wafer or die bonding, which could be wafer-to-wafer (W2W) bonding or die-to-wafer (D2W) bonding.
Wafer thinning is used to reduce the impact of TSVs. The thinner the wafer, the smaller (and shorter) the TSV is (with the same aspect ratio constraint). The wafer thickness could be in the range of 10 to 100$\mu$ mm and the TSV size is in the range of 0.2 to 10$\mu$mm .
In TSV-based 3D stacking bonding, the dimension of the TSVs is not expected to scale at the same rate as feature size because alignment tolerance during bonding poses limitation on the scaling of the vias. The TSV size, length, and the pitch density, as well as the bonding method (face-to-face or face-to-back bonding, SOIbased 3D or bulk CMOS-based 3D), can have a significant impact on the 3D microprocessor design. For example, relatively large size of TSVs can hinder partitioning a design at fine granularity across multiple device layers and make the true 3D component design less possible. On the other hand, the monolithic 3D integration provides more flexibility in vertical 3D connection because the vertical 3D via can potentially scale down with feature size due to the use of local wires for connection. Availability of such technologies makes it possible to partition the design at a very fine granularity. Furthermore, face-to-face bonding or SOI-based 3D integration may have a smaller via pitch size and higher via density than face-to-back bonding or bulk-CMOS-based integration. Such influence of the 3D technology parameters on the microprocessor design must be thoroughly studied before an appropriate partition strategy is adopted.